Rainbow Electronics MAX3627 - Manual (Page 7)

MAX3627
+3.3V, Low-Jitter, Precision Clock
Generator with Multiple Outputs
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Pin Description
PIN NAME FUNCTION
1 Q0 LVDS, Noninverting Clock Output
2 Q0 LVDS, Inverting Clock Output
3, 9, 24, 32 GND Supply Ground
4 Q1 LVDS, Noninverting Clock Output
5 Q1 LVDS, Inverting Clock Output
6, 12, 19 V DDO_DIFF Power Supply for Q0, Q1, Q2, Q3, Q4, Q5, and Q6 Clock Outputs. Connect to +3.3V.
7 Q2 LVDS, Noninverting Clock Output
8 Q2 LVDS, Inverting Clock Output
10 Q3 LVDS, Noninverting Clock Output
11 Q3 LVDS, Inverting Clock Output
13 Q4 LVDS, Noninverting Clock Output
14 Q4 LVDS, Inverting Clock Output
15 FSELB
Three-State LVCMOS/LVTTL Input. Controls the Q1 to Q7 output divider. When connected to logic-
low, the output frequency is 125MHz. When connected to logic-high, the output frequency is
156.25MHz. When left open (high-Z), the output frequency is 312.5MHz. For the Q7 LVCMOS output,
the output specification is only valid up to 160MHz.
16 OE
LVCMOS/LVTTL Input. Enable/disable control for the Q4, Q5, and Q6 outputs. The OE pin has an
internal 75k
pullup resistor. When OE is connected to V
DD or left open, Q4, Q5, and Q6 are enabled.
When OE is connected to GND, Q4, Q5, and Q6 are disabled to reduce power consumption. When
disabled, Q4, Q5, and Q6 are high impedance.
17 Q5 LVDS, Noninverting Clock Output
18 Q5 LVDS, Inverting Clock Output
20 Q6 LVDS, Noninverting Clock Output
21 Q6 LVDS, Inverting Clock Output
22 V DDO_SE Power Supply for Q7 Clock Output. Connect to +3.3V.
23 Q7 LVCMOS Clock Output
25 V DD Core Power Supply. Connect to +3.3V.
26 PLL_BP
Three-State LVCMOS/LVTTL Input (Active Low). When connected to logic-high, the PLL locks to the
crystal interface (25MHz typical at X_IN and X_OUT). When left open (high-Z), the PLL locks to the
OSC_IN input (25MHz typical). When connected to logic-low, the PLL is bypassed and the OSC_IN
input is selected. When bypass mode is selected, the VCO/PLL is disabled to save power and
eliminate intermodulation spurs.
27 V DDA
Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this
pin can be connected to V
DD through a 10.5 resistor as shown in Figure 4.
28 FSELA
Three-State LVCMOS/LVTTL Input. Controls the Q0 output divider. When connected to logic-low, the
output frequency is 125MHz. When connected to logic-high, the output frequency is 156.25MHz.
When left open (high-Z), the output frequency is 312.5MHz.
29 OSC_IN
LVCMOS Input. Self-biased to allow AC- or DC-coupling. When PLL_BP is open, the OSC_IN input
frequency should be 25MHz. When the PLL is in bypass mode ( PLL_BP = low), the OSC_IN input
frequency can be between 20MHz and 320MHz. When PLL_BP is high, the OSC_IN should be
disconnected.
30 X_IN Crystal Oscillator Input
31 X_OUT Crystal Oscillator Output
— EP Exposed Pad. Connect to GND for proper electrical and thermal performance.