Rainbow Electronics DS2502 - Manual (Page 13)

DS2502
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contains 0s in the same bit positions as the data byte, the programming was successful and the DS2502
will automatically increment its address counter to select the next byte in the EPROM Status data field.
The least significant byte of the new 2-byte address will also be loaded into the 8-bit CRC generator as a
starting value. The bus master will issue the next byte of data using eight write time slots.
As the DS2502 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator
that has been preloaded with the LSB of the current address and the result is an 8-bit CRC of the new data
byte and the LSB of the new address. After supplying the data byte, the bus master will read this 8-bit
CRC from the DS2502 with eight read time slots to confirm that the address incremented properly and the
data byte was received correctly. If the CRC is incorrect, a reset pulse must be issued and the Write Status
command sequence must be restarted. If the CRC is correct, the bus master will issue a programming
pulse and the selected byte in memory will be programmed.
Note that the initial pass through the Write Status flow chart will generate an 8-bit CRC value that is the
result of shifting the command byte into the CRC generator, followed by the 2 address bytes, and finally
the data byte. Subsequent passes through the Write Status flow chart due to the DS2502 automatically
incrementing its address counter will generate an 8-bit CRC that is the result of loading (not shifting) the
LSB of the new (incremented) address into the CRC generator and then shifting in the new data byte.
For both of these cases, the decision to continue (to apply a program pulse to the DS2502) is made
entirely by the bus master, since the DS2502 will not be able to determine if the 8-bit CRC calculated by
the bus master agrees with the 8-bit CRC calculated by the DS2502. If an incorrect CRC is ignored and a
program pulse is applied by the bus master, incorrect programming could occur within the DS2502. Also
note that the DS2502 will always increment its internal address counter after the receipt of the eight read
time slots used to confirm the programming of the selected EPROM byte. The decision to continue is
again made entirely by the bus master, therefore if the EPROM data byte does not match the supplied
data byte but the master continues with the Write Status command, incorrect programming could occur
within the DS2502. The Write Status command sequence can be ended at any point by issuing a reset
pulse.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances, the
DS2502 is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal type and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an
open drain connection or three-state outputs. The DS2502 is an open drain part with an internal circuit
equivalent to that shown in Figure 7. The bus master can be the same equivalent circuit. If a bi-directional
pin is not available, separate output and input pins can be tied together.
The bus master requires a pullup resistor at the master end of the bus, with the bus master circuit
equivalent to the one shown in Figures 8a and 8b. The value of the pullup resistor should be
approximately 5 k? for short line lengths.