Rainbow Electronics DS1957 - Manual (Page 13)

DS1957
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READ STATUS [E1H]
In addition to the Intermediate Product Register (IPR) and the I/O buffer for data exchange and exchange
management respectively, the DS1957 provides several bytes of status information. These status bytes
manage the use of the I/O buffer, signal the availability of resources and the progress of numerical
calculations, pass bit-level information to control the program flow within the microcomputer and return
bit-level responses. The bus master can read a total of four bytes and can write one byte of status
information. The status register names are OWMS (1-Wire Micro Status), CPST (Accelerator Status) and
OWUS (1-Wire UART Status).
After the command code for Read Status the bus master will read a total of six bytes. The first byte tells
the number of free bytes in the input section of the I/O buffer. This number may be anywhere from 00H
to 08H with the 00H standing for a full and the 08H for an empty buffer. The next byte tells the number
of used (valid) bytes in the output section of the I/O buffer. This number ranges from 00H to 08H with
the 00H standing for an empty and the 08H for a full buffer. The next two bytes are the 1-Wire Micro
Status (OWMS) and the Accelerator Status (CPST). The remaining two bytes of the sequence are the
inverted CRC16 over the Read Status command code and the four bytes of status information.
Both the OWMS and CPST are read-only for the bus master. The lower six bits of the OWMS signal
various conditions and bit-level responses from the microcomputer inside the DS1957. The details on the
use of these bits are explained in the “Crypto iButton Firmware Reference Manual.” Bit 6 (BPOR)
signals power failures. Bit 7 (IOST) indicates the availability of the Intermediate Product Register for
reading/writing data through the 1-Wire bus. Depending on the status of the program, the IPR may
temporarily be locked for exclusive use by the arithmetic accelerator.
OWMS REGISTER
The read-only CPST register directly interfaces to the accelerator’s control logic. The upper seven bits of
the CPST register represent the seven most significant bits of the accelerator’s 11 bit exponentiation
counter. Bit 0 of CPST is the logical OR of all bits of this counter. At the beginning of a numerical
calculation, the exponentiation counter starts at a high number and decrements. The lower the number in
the CPST register, the further the calculation has progressed. The calculation is finished when CPST
reads 00H.
IOST
7 6 5 4 3 2 1 0
BPOR 6
7
0 = normal operation
1 = indicates power failure
STAT3 STAT2 STAT1 STAT0 BPOR STAT5 STAT4
IOST
0 = bus master may access the
I/O buffer as well as the IPR
1 = bus master can only access
the I/O buffer