Rainbow Electronics HT49R70A-1 - Manual (Page 30)

CLR [m].i Clear bit of data memory
Description The bit i of the specified data memory is cleared to 0.
Operation [m].i ¬ 0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾
CLR WDT Clear Watchdog Timer
Description The WDT and the WDT Prescaler are cleared (re-counting from 0). The power down bit
(PD) and time-out bit (TO) are cleared.
Operation WDT and WDT Prescaler ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ 0 0 ¾ ¾ ¾ ¾
CLR WDT1 Preclear Watchdog Timer
Description The TO, PD flags, WDT and the WDT Prescaler has cleared (re-counting from 0), if the
other preclear WDT instruction has been executed. Only execution of this instruction with-
out the other preclear instruction just sets the indicated flag which implies this instruction
has been executed and the TO and PD flags remain unchanged.
Operation WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ 0* 0* ¾ ¾ ¾ ¾
CLR WDT2 Preclear Watchdog Timer
Description The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting from 0), if the
other preclear WDT instruction has been executed. Only execution of this instruction with-
out the other preclear instruction, sets the indicated flag which implies this instruction has
been executed and the TO and PD flags remain unchanged.
Operation WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ 0* 0* ¾ ¾ ¾ ¾
CPL [m] Complement data memory
Description Each bit of the specified data memory is logically complemented (1 ¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation [m] ¬ [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾
HT49R70A-1
Rev. 1.00 30 December 4, 2001