Rainbow Electronics HT49R70A-1 - Manual (Page 11)

HT49R70A-1
Rev. 1.00 11 December 4, 2001
gram which corrupts the desired control sequence, the
contents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of INT0 or INT1, and the related interrupt request
flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as
well. After the interrupt is enabled, the stack is not full,
and the external interrupt is active, a subroutine call to
location 04H or 08H occurs. The interrupt request flag
(EIF0 or EIF1) and EMI bits are all cleared to disable
other interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 6 of INTC0), which is normally
caused by a timer overflow. After the interrupt is en-
abled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 0CH occurs. The related inter-
rupt request flag (T0F) is reset, and the EMI bit is
cleared to disable further interrupts. The Timer/Event
Counter 1 is operated in the same manner but its related
interrupt request flag is T1F (bit 4 of INTC1) and its sub-
routine call location is 10H.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC1), that is
caused by a regular time base signal. After the interrupt
is enabled, and the stack is not full, and the TBF bit is
set, a subroutine call to location 14H occurs. The related
interrupt request flag (TBF) is reset and the EMI bit is
cleared to disable further interrupts.
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 6 of
INTC1), that is caused by a regular real time clock sig-
nal. After the interrupt is enabled, and the stack is not
full, and the RTF bit is set, a subroutine call to location
18H occurs. The related interrupt request flag (RTF) is
reset and the EMI bit is cleared to disable further inter-
rupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are all held until the ²RETI²
instruction is executed or the EMI bit and the related in-
terrupt control bit are set both to 1 (if the stack is not full).
To return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI sets the EMI bit and enables an
interrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
No. Interrupt Source Priority Vector
a External interrupt 0 1 04H
b External interrupt 1 2 08H
c Timer/Event Counter 0 overflow 3 0CH
d Timer/Event Counter 1 overflow 4 10H
e Time base interrupt 5 14H
f Real time clock interrupt 6 18H
Register Bit No. Label Function
INTC0
(0BH)
0 EMI Control the master (global) interrupt (1=enabled; 0=disabled)
1 EEI0 Control the external interrupt 0 (1=enabled; 0=disabled)
2 EEI1 Control the external interrupt 1 (1=enabled; 0=disabled)
3 ET0I Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
4 EIF0 External interrupt 0 request flag (1=active; 0=inactive)
5 EIF1 External interrupt 1 request flag (1=active; 0=inactive)
6 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
7 ¾ Unused bit, read as ²0²
INTC1
(1EH)
0 ET1I Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
1 ETBI Control the time base interrupt (1=enabled; 0:disabled)
2 ERTI Control the real time clock interrupt (1=enabled; 0:disabled)
3 ¾ Unused bit, read as ²0²
4 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
5 TBF Time base request flag (1=active; 0=inactive)
6 RTF Real time clock request flag (1=active; 0=inactive)
7 ¾ Unused bit, read as ²0²
INTC register