Rainbow Electronics DS1682 - Manual (Page 9)

DS1682
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Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain HIGH.
Start Data Transfer: A change in the state of the data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
Stop Data Transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data Valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit. Within the bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz
clock rate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after it
receives each byte. The master device must generate an extra clock pulse, which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of
course, setup and hold times must be considered. A master must signal an end-of-data to the slave by not
generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the
slave must leave the data line HIGH to enable the master to generate the STOP condition.
Depending upon the state of the R/W bit, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. A “not acknowledge” is returned at the end of the last received byte.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.