Rainbow Electronics DS1315 - Manual (Page 5)

DS1315
041697 5/22
When the ROM/RAM pin is connected to V
CCO
, the con-
troller is set in the ROM mode. Since ROM is a read–
only device that retains data in the absence of power,
battery backup and write protection is not required. As a
result, the chip enable logic will force CEO low when
power fails. However, the Time Chip does retain the
same internal nonvolatility and write protection as de-
scribed in the RAM mode. A typical ROM/Time Chip in-
terface is illustrated in Figure 4.
DS1315 TO RAM/TIME CHIP INTERFACE Figure 3
CMOS STATIC RAM
A0 – AN
DATA I/O
WE
OE
CE
DS1315
CEO
OE
WE
CEI
RST
BAT 1
X 1
BAT 2
X 2
V CCO
D
Q
V CCI
ROM/
RAM
+ +
BAT 1 BAT 2
32.768 KHz
A0 – AN
D0 – D7
CE
RST
V CC
1 2
V CC
WE
OE