Rainbow Electronics DS2405 User Manual
Page 15
DS2405
15 of 15
NOTES:
1. All voltages are referenced to ground.
2. V
PUP
= external pullup voltage.
3. Input load is to ground.
4. An additional reset or communication sequence cannot begin until the reset high time has expired.
5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1
ms of this falling edge and will remain valid for 14ms minimum (15ms
total from falling edge on 1-Wire bus).
6. V
IH
is a function of the external pull-up resistor and the V
CC
supply.
7. Capacitance on the data pin could be 800pF when power is first applied. If a 5k
W resistor is used to
pull-up the data line to V
CC
, 5
ms after power has been applied the parasite capacitance will not affect
normal communications.
8. V
IH
for PIO pin should always be greater than or equal to V
PUP
-0.3V.
9. Input resistance is to ground.
10. Under certain low voltage conditions V
ILMAX
may have to be reduced to as much as 0.5V to always
guarantee a Presence Pulse.
11. The optimal sampling point for the master is as close as possible to the end of the 15µs t
RDV
period
without exceeding t
RDV.
For the case of a Read 1 time slot, this maximizes the amount of time for the
pull-up resistor to recover the line to a high level. For a Read 0 time slot, it ensures that a read will
occur before the fastest 1-Wire device(s) release the line.
12. The duration of the low pulse sent by the master should be a minimum of 1µs with a maximum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write 1 Low Time, or before the master samples in the case of
a Read Low Time.
13. The Reset Low Time (t
RSTL
) should be restricted to a maximum of 960µs to allow interrupt signaling;
otherwise, it could mask or conceal interrupt pulses.