Rainbow Electronics DS2405 - Manual (Page 12)

DS2405
12 of 15
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 6. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2405 to the master
by triggering a delay circuit in the DS2405. During write time slots, the delay circuit determines when the
DS2405 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2405 will hold the data line low overriding the “1” generated by the master.
If the data bit is a 1, the device will leave the read data time slot unchanged.
READ/WRITE TIMING DIAGRAM Figure 6
Write-1 Time Slot
60 ms £ t
SLOT
< 120 ms
1 ms £ t
LOW1
< 15 ms
1 ms £ t
REC
< ¥
Write-0 Time Slot
60 ms £ t
LOW0
< t
SLOT
< 120 ms
1 ms £ t
REC
< ¥
RESISTOR
MASTER