Rainbow Electronics MAX8728 - Manual (Page 26)

MAX8728
Low-Cost, Multiple-Output
Power Supply for LCD Monitors/TVs
26 ______________________________________________________________________________________
Charge-Pump Output Capacitor
Decreasing the flying capacitance reduces the output
ripple. Increasing the output capacitance reduces the
output ripple and improves the transient response. Use
the following equations to approximate the output ripple:
where V OUT_POS is the positive charge-pump output
voltage, C X_POS is the flying capacitor of the positive
charge pump, C OUT_POS is the output capacitor of the
positive charge-pump, V OUT_NEG is the negative
charge-pump output voltage, CX_NEG is the flying
capacitor of the negative charge pump, and C OUT_NEG
is the output capacitor of the negative charge pump.
Output-Voltage Selection
Adjust the positive charge-pump regulator’s output volt-
age by connecting a resistive voltage-divider from SRC
to GND with the center tap connected to FBP (Figure 1).
Select the lower resistor of divider R7 in the 10k
Ω to
30k
Ω range. Calculate upper resistor R8 with the follow-
ing equation:
where V
FBP
= 2V (typ). Adding a small capacitor
(e.g., 10pF) across R7 reduces pulse grouping and
output noise.
Adjust the negative charge-pump regulator’s output
voltage by connecting a resistive voltage-divider from
V
GOFF to REF with the center tap connected to FBN
(Figure 1). Select R9 in the 35k
Ω to 68kΩ range.
Calculate R10 with the following equation:
where V FBN = 250mV, V REF = 12V. Note that REF can
only source up to 50µA; using a resistor less than 35k Ω
for R9 results in higher bias current than REF can supply.
PC Board Layout and Grounding
Careful PC board layout is important for proper operation.
Use the following guidelines for good PC board layout:
1) Minimize the area of respective high-current loops
by placing each DC-DC converter’s inductor, diode,
and output capacitors near its input capacitors and
its LX_ and GND_ pins. For the step-down regulator,
the high-current input loop goes from the positive
terminal of the input capacitor to the IC’s IN pin, out
of LX1, to the inductor, to the positive terminals of
the output capacitors, reconnecting the output
capacitor and input capacitor ground terminals. The
high-current output loop is from the inductor to the
positive terminals of the output capacitors, to the
negative terminals of the output capacitors, and to
the Schottky diode (D2). For the step-up regulator,
the high-current input loop goes from the positive
terminal of the input capacitor to the inductor, to the
IC’s LX2 pin, out of GND2, and to the input capaci-
tor’s negative terminal. The high-current output loop
is from the positive terminal of the input capacitor to
the inductor, to the output diode (D1), to the positive
terminal of the output capacitors, reconnecting
between the output capacitor and input capacitor
ground terminals. Connect these loop components
with short, wide connections. Avoid using vias in the
high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
2) Create a power ground island (GND1) for the step-
down regulator, consisting of the input and output
capacitor grounds and the GND1 pin. Connect all
these together with short, wide traces or a small
ground plane. Similarly, create a power ground
island (GND2) for the step-up regulator, consisting
of the input and output capacitor grounds and the
GND2 pin. Maximizing the width of the power
ground traces improves efficiency and reduces out-
put voltage ripple and noise spikes. Create an ana-
log ground plane (GND) consisting of the GND pin,
all the feedback-divider ground connections, the
COMP and DEL capacitor ground connections, and
the device’s exposed backside pad, with a large
area of in-the-layer or solder-side copper with large
or multiple vias to the backside pad to cool the IC.
Connect the GND1, GND2, and GND islands by
connecting the three ground pins directly to the
exposed backside pad. Make no other connections
between these separate ground planes.
R R
V V
V V
FBN GOFF
REF FBN
10 9
= ×
−
−
R R
V
V
GON
FBP
7 8 1 = × −
⎛
⎝⎜ ⎞
⎠⎟
V
n x V x n x V V
n
X
C
C
V
n x V x n x V V
n
X
C
C
RIPPLE POS
POS SUPP POS D OUT POS
POS
X POS
OUT POS
RIPPLE NEG
NEG SUPP NEG D OUT NEG
NEG
X NEG
OUT NEG
_
_
_
_
_
_
_
_
( )
=
+ − − ⎡
⎣
⎢
⎤
⎦
⎥
=
− + ⎡
⎣
⎢
⎤
⎦
⎥
1 2
2