Rainbow Electronics MAX8728 - Manual (Page 23)

MAX8728
Low-Cost, Multiple-Output
Power Supply for LCD Monitors/TVs
______________________________________________________________________________________ 23
Output-Capacitor Selection
Since the MAX8728’s step-down regulator is internally
compensated, it is stable with any reasonable amount
of output capacitance. However, the actual capaci-
tance and equivalent series resistance (ESR) affect the
regulator’s output ripple voltage and transient
response. The rest of this section deals with how to
determine the output capacitance and ESR needs
according to the ripple voltage and load-transient
requirements.
The output voltage ripple has two components: varia-
tions in the charge stored in the output capacitor, and
the voltage drop across the capacitor’s ESR caused by
the current into and out of the capacitor:
where I OUT1 _ RIPPLE is defined in the Step-Down
Regulator, Inductor Selection section, C OUT1 is output
capacitance, and R ESR _ OUT1 is the ESR of output
capacitor C OUT1 . In Figure 1’s circuit, the inductor rip-
ple current is 0.6A. If the voltage ripple requirement of
Figure 1’s circuit is ±1% of the 3.3V output, then the
total peak-to-peak ripple voltage should be less than
66mV. Assuming that the ESR ripple and the capacitive
ripple each should be less than 50% of the total peak-
to-peak ripple, then the ESR should be less than 55m
Ω
and the output capacitance should be more than 1.5µF
to meet the total ripple requirement. A 22µF capacitor
with ESR (including PC board trace resistance) of 10m
Ω
is selected for the standard application circuit in Figure 1,
which easily meets the voltage-ripple requirement.
The step-down regulator’s output capacitor and ESR
also affect the voltage undershoot and overshoot when
the load steps up and down abruptly. The undershoot
and overshoot also have two components: the voltage
steps caused by ESR and voltage sag and soar due to
the finite capacitance and inductor slew rate. Use the
following formulae to check if the ESR is low enough
and the output capacitance is large enough to prevent
excessive soar and sag.
The amplitude of the ESR step is a function of the load
step and the ESR of the output capacitor:
V OUT1_ESR_STEP =
ΔI
OUT1 x R ESR_OUT1
The amplitude of the capacitive sag is a function of the
load step, the output capacitor value, the inductor
value, the input-to-output voltage differential, and the
maximum duty cycle:
The amplitude of the capacitive soar is a function of the
load step, the output capacitor value, the inductor
value and the output voltage:
Given the component values in the circuit of Figure 1,
during a 2A step-load transient, the voltage step due to
capacitor ESR is negligible. The voltage sag and soar
are 40.2mV and 71.6mV, respectively.
Rectifier Diode
The MAX8728’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommended
for most applications because of their fast recovery time
and low forward voltage. In general, a 2A Schottky
diode works well in the MAX8728’s step-down regulator.
Output-Voltage Selection
Connect a resistive voltage-divider between OUT1 and
GND with the center tap connected to FB1 to adjust the
output voltage. Choose R12 (resistance from FB1 to
GND) to be between 5k
Ω and 50kΩ, and solve for R11
(resistance from OUT1 to FB1) using the equation:
where V
FB1
= 2V, and V
OUT1
may vary from 2V to 3.6V.
Connecting a small capacitor (e.g., 47pF) between FB1
and GND reduces FB1 noise sensitivity.
Step-Up Regulator Design
Inductor Selection
The inductance value, peak-current rating, and series
resistance are factors to consider when selecting the
step-up inductor. These factors influence the convert-
er’s efficiency, maximum output load capability, tran-
sient response time, and output voltage ripple. Physical
size and cost are also important factors to be consid-
ered.
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high inductance values minimize the cur-
R R
V
V
OUT
FB
11 12 1
1
1
= × −
⎛
⎝⎜ ⎞
⎠⎟
V
L I
C V
OUT SOAR
OUT OUT
OUT OUT
1
1 1
2
1 1
2
_
( )
=
Ч
Ч Ч
Δ
V
L I
C V D V
OUT SAG
OUT OUT
OUT IN MIN MAX OUT
1
1 1
2
1 1
2
_
( )
( )
=
Ч
Ч Ч Ч −
( )
Δ
V V V
V I R
V
I
C f
OUT RIPPLE OUT RIPPLE ESR OUT RIPPLE C
OUT RIPPLE ESR OUT RIPPLE ESR OUT
OUT RIPPLE C
OUT RIPPLE
OUT SW
1 1 1
1 1 1
1
1
1
8
_ _ ( ) _ ( )
_ ( ) _ _
_ ( )
_
= +
= Ч
=
Ч Ч