Rainbow Electronics ADC08161 - Manual (Page 10)

Pin Description
(Continued)
WR /RDY WR -RD Mode (Logic high applied to MODE
pin)
WR : With CS low, the conversion is started on
the rising edge of WR . The digital result will be
strobed into the output latch at the end of con-
version (
Figures 2, 3, 4 ).
RD Mode (Logic low applied to MODE pin)
RDY: This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and returns high at the end of con-
version.
MODE Mode: Mode (RD or WR -RD ) selection input–
This pin is pulled to a logic low through an inter-
nal 50 µA current sink when left unconnected.
RD Mode is selected if the MODE pin is left un-
connected or externally forced low. A complete
conversion is accomplished by pulling RD low
until output data appears.
WR -RD Mode is selected when a high is ap-
plied to the MODE pin. A conversion starts with
the WR signal’s rising edge and then using RD
to access the data.
RD WR -RD Mode (logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DB0–DB7) will be activated when RD
goes low (
Figures 2, 3, 4 ).
RD Mode (logic low on the MODE pin)
With CS low, a conversion starts on the
falling edge of RD . Output data appears
on DB0–DB7 at the end of conversion
(
Figures 1, 5 ).
INT This is an active low output that indicates
that a conversion is complete and the data
is in the output latch. INT is reset by the
rising edge of RD .
GND This is the power supply ground pin. The
ground pin should be connected to a
“clean” ground reference point.
V
REF−
, V
REF+
These are the reference voltage inputs.
They may be placed at any voltage be-
tween GND − 50 mV and V
+ + 50 mV, but
V
REF+
must be greater than V
REF−
. Ideally,
an input voltage equal to V
REF−
produces
an output code of 0, and an input voltage
greater than V
REF+
− 1.5 LSB produces an
output code of 255.
For the ADC08161 an input voltage that
exceeds V
+ by more than 100 mV or is be-
low GND by more than 100 mV will create
conversion errors.
CS This is the active low Chip Select input. A
logic low signal applied to this input pin en-
ables the RD and WR inputs. Internally,
the CS signal is ORed with RD and WR
signals.
OFL Overflow Output. If the analog input is
higher than V
REF+
, OFL will be low at the
end of conversion. It can be used when
cascading two ADC08161s to achieve
higher resolution (9 bits). This output is al-
ways
active and does not go into
TRI-STATE as DB0–DB7 do. When OFL
is set, all data outputs remain high when
the ADC08061’s output data is read.
V + Positive power supply voltage input. Nomi-
nal operating supply voltage is +5V. The
supply pin should be bypassed with a 10
µF bead tantalum in parallel with a 0.1 ce-
ramic capacitor. Lead length should be as
short as possible.
V
REFOUT
The internal bandgap reference’s 2.5V
output is available on this pin. Use a 220
µF bypass capacitor between this pin and
analog ground.
www.national.com 10