Rainbow Electronics MAX15051 - Manual (Page 12)

MAX15050/MAX15051
High-Efficiency, 4A, 1MHz, Step-Down Regulators
with Integrated Switches in 2mm x 2mm Package
The peak-to-peak inductor current (I P-P ) is:
Use these equations for initial output-capacitor selec-
tion. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output-voltage rip-
ple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x
∆I
LOAD . Before the con-
troller can respond, the output deviates further,
depending on the inductor and output capacitor val-
ues. After a short time, the controller responds by regu-
lating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviat-
ing further from its regulating value. See the
Compen-
sation Design section for more details. The minimum
recommended output capacitance for the MAX15051
and MAX15051 is 47µF and 22µF, respectively.
Input-Capacitor Selection
When transitioning from skip mode to PWM mode
(MAX15050) with a large current load step, additional out-
put capacitance can be used to help minimize the load-
transient response. The input capacitor reduces the
current peaks drawn from the input power supply and
reduces switching noise in the device. The total input
capacitance must be equal to or greater than the value
given by the following equation to keep the input ripple
voltage within the specification and minimize the high-fre-
quency ripple current being fed back to the input source:
where V IN-RIPPLE is the maximum-allowed input ripple
voltage across the input capacitors and is recommend-
ed to be less than 2% of the minimum input voltage, D
is the duty cycle (V
OUT
/V
IN
), T
S
is the switching period
(1/f S ) = 1µs, and I OUT is the output load.
The impedance of the input capacitor at the switching fre-
quency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
where I RIPPLE is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the
inductor, L, and the output capacitor, C
O . The ESR of the
output capacitor determines the zero. The double pole
and zero frequencies are given as follows:
where R
L
is equal to the sum of the output inductor’s DC
resistance (DCR) and the internal switch resistance,
R
DS(ON) . A typical value for R DS(ON) is 25m Ω. R
O is the
output load resistance, which is equal to the rated output
voltage divided by the rated output current. ESR is the
total equivalent series resistance of the output capacitor. If
there is more than one output capacitor of the same type
in parallel, the value of the ESR in the above equation is
equal to that of the ESR of a single output capacitor divid-
ed by the total number of output capacitors.
The MAX15050/MAX15051 high switching frequency
allows the use of ceramic output capacitors. Since the ESR
of ceramic capacitors is typically very low, the frequency of
the associated transfer function zero is higher than the
unity-gain crossover frequency, f
C , and the zero cannot be
used to compensate for the double pole created by the
output inductor and capacitor. The double pole produces
a gain drop of 40dB/decade and a phase shift of 180°. The
compensation network must compensate for this gain drop
and phase shift to achieve a stable high-bandwidth closed-
loop system. Therefore, use type III compensation as
shown in Figure 4 and Figure 5. Type III compensation
possesses three poles and two zeros with the first pole,
f
P1_EA
, located at zero frequency (DC). Locations of other
poles and zeros of the type III compensation are given by:
f
x R x C
Z EA 2
1
2 3 3
_
=
π
f
x R x C
Z EA 1
1
2 1 1
_
=
π
f
x ESR x C
Z ESR
O
_
=
1
2 π
f f
x L x C x
R ESR
R R
P LC P LC
O
O
O L
1 2
1
2
_ _
= =
+
+
⎛
⎝⎜ ⎞
⎠⎟
π
I I
V V V
V
RIPPLE LOAD
OUT IN OUT
IN
= Ч
Ч − ( )
C
D x T x I
V
IN MIN
S OUT
IN RIPPLE
_
=
−
I
V V
f L
x
V
V
P P
IN OUT
S
OUT
IN
−
=
−
Ч
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