Rainbow Electronics ADC12038 - Manual (Page 8)

AC Electrical Characteristics
(Continued)
The following specifications apply for V a e V
A
a e V
D
a e a 5 0 V
DC
V
REF
a e a 4 096 V
DC
V
REF
b e 0 V
DC
12-bit a
sign conversion mode t r e t f e 3 ns f CK e f SK e 8 MHz for the ADC12H030 ADC12H032 ADC12H034 and ADC12H038
f CK e f SK e 5 MHz for the ADC12030 ADC12032 ADC12034 and ADC12038 R S e 25X source impedance for V REF a and
V
REF
b s 25X fully-differential input with fixed 2 048V common-mode voltage and 10(t
CK
) acquisition time unless otherwise
specified Boldface limits apply for T
A e T
J e T
MIN
to T
MAX
all other limits T
A e T
J e 25 C (Note 17)
Symbol Parameter Conditions
Typical Limits Units
(Note 10) (Note 11) (Limits)
t HPU Hardware Power-Up Time Time from
140 250 m s (max)
PD Falling Edge to EOC Rising Edge
t
SPU
Software Power-Up Time Time from
Serial Data Clock Falling Edge to
140 250 m s (max)
EOC Rising Edge
t
ACC
Access Time Delay from
20 50 ns (max)
CS Falling Edge to DO Data Valid
t
SET-UP
Set-Up Time of CS Falling Edge to
30 ns (min)
Serial Data Clock Rising Edge
t DELAY Delay from SCLK Falling
0 5 ns (min)
Edge to CS Falling Edge
t 1H t 0H Delay from CS Rising Edge to R L e 3k C L e 100 pF
40 100 ns (max)
DO TRI-STATE
t HDI DI Hold Time from Serial Data
5 15 ns (min)
Clock Rising Edge
t SDI DI Set-Up Time from Serial Data
5 10 ns (min)
Clock Rising Edge
t HDO DO Hold Time from Serial Data R L e 3k C L e 100 pF
25
50 ns (max)
Clock Falling Edge 5 ns (min)
t DDO Delay from Serial Data Clock
35 50 ns (max)
Falling Edge to DO Data Valid
t RDO DO Rise Time TRI-STATE to High R L e 3k C L e 100 pF 10 30 ns (max)
DO Rise Time Low to High 10 30 ns (max)
t FDO DO Fall Time TRI-STATE to Low R L e 3k C L e 100 pF 12 30 ns (max)
DO Fall Time High to Low 12 30 ns (max)
t CD Delay from CS Falling Edge
25 45 ns (max)
to DOR Falling Edge
t SD Delay from Serial Data Clock Falling
25 45 ns (max)
Edge to DOR Rising Edge
C
IN
Capacitance of Logic Inputs 10 pF
C OUT Capacitance of Logic Outputs 20 pF
8