3 0 applications information – Rainbow Electronics ADC10158 User Manual

Page 20

3 0 Applications Information

(Continued)

The minimum value of V

REF

)

can be quite small (see Typical Performance Characteris-
tics) to allow direct conversion of transducer outputs provid-
ing less than a 5V output span Particular care must be tak-
en with regard to noise pickup circuit layout and system
error voltage sources when operating with a reduced span
due to the increased sensitivity of the converter (1 LSB
equals V

REF

)

3 3 THE ANALOG INPUTS

Due to the sampling nature of the analog inputs at the clock
edges short duration spikes of current will be seen on the
selected assigned negative input Input bypass capacitors
should not be used if the source resistance is greater than
1 kX since they will average the AC current and cause an
effective DC current to flow through the analog input source
resistance An op amp RC active lowpass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required Bypass capacitors
may be used when the source impedance is very low with-
out any degradation in performance

In a true differential input stage a signal that is common to
both ‘‘a’’ and ‘‘b’’ inputs is cancelled For the ADC10154
and ADC10158 the positive input of a selected channel pair
is only sampled once before the start of a conversion during
the acquisition time (t

) The negative input needs to be

stable during the complete conversion sequence because it
is sampled before each decision in the SAR sequence
Therefore any AC common-mode signal present on the an-
alog inputs will not be completely cancelled and will cause
some conversion errors For a sinusoid common-mode sig-
nal this error is

error

(Max) e V

PEAK

)(t

)

where f

is the frequency of the common-mode signal

PEAK

is its peak voltage value and t

is the A D’s maxi-

mum conversion time (t

22 f

CLK

for 10-bit plus sign

resolution) For example for a 60 Hz common-mode signal
to generate a

LSB error (1 24 mV) with a 4 5 ms conver-

sion time its peak value would have to be approximately
731 mV

3 4 OPTIONAL ADJUSTMENTS

3 4 1 Zero Error

The zero error of the A D converter relates to the location
of the first riser of the transfer function (see

Figure 1

) and

can be measured by grounding the minus input and applying
a small magnitude positive or negative voltage to the plus
input Zero error is the difference between actual DC input
voltage which is necessary to just cause an output digital
code transition from 000 0000 0000 to 000 0000 0001 (10-
bits plus sign) and the ideal

LSB value (

LSB e 2 44

mV for V

REF

e a

5 000V and 10-bit plus sign resolution)

The zero error of the A D does not require adjustment If
the minimum analog input voltage value V

(Min) is not

ground the effetive ‘‘zero’’ voltage can be adjusted to a
convenient value The converter can be made to output an
all zeros digital code for this minimum input voltage by bias-
ing any minus input to V

(Min) This is useful for either the

differential or pseudo-differential input channel configura-
tions

3 4 2 Full-Scale

The full-scale adjustment can be made by applying a differ-
ential input voltage which is 1

LSB down from the desired

analog full-scale voltage range and then adjusting the V

REF

voltage (V

REF

) for a digital output

code changing from 011 1111 1110 to 011 1111 1111 In
bipolar signed operation this only adjusts the positive full
scale error The negative full-scale error will be as specified
in the Electrical Characteristics after a positive full-scale ad-
justment

3 4 3 Adjusting for an Arbitrary Analog Input
Voltage Range

If the analog zero voltage of the A D is shifted away from
ground (for example to accommodate an analog input sig-
nal which does not go to ground) this new zero reference
should be properly adjusted first A plus input voltage which
equals this desired zero reference plus

LSB (where the

LSB is calculated for the desired analog span using 1 LSB

analog span 2

n being the programmed resolution) is

applied to selected plus input and the zero reference volt-
age at the corresponding minus input should then be adjust-
ed to just obtain the 000

HEX

to 001

HEX

code transition

The full-scale adjustment should be made with the proper
minus input voltage applied by forcing a voltage to the plus
input which is given by

(a) fs adj e V

MAX

1 5

MAX

MIN

)

(

where V

MAX

equals the high end of the ananlog input range

MIN

equals the low end (the offset zero) of the analog

range and n equals the programmed resolution Both V

MAX

and V

MIN

are ground referred The V

REF

) voltage is then adjusted to provide a code

change from 3FE

HEX

to 3FF

HEX

Note when using a pseu-

do-differential or differential multiplexer mode where V

REF

and V

REF

are placed within the V

and V

range the

individual values of V

REF

and V

REF

do not matter only

the difference sets the analog input voltage span This com-
pletes the adjustment procedure

3 5 INPUT SAMPLE-AND-HOLD

The ADC10154 8’s sample hold capacitor is implemented
in the capacitor array After the channel address is loaded
the array is switched to sample the selected positive analog
input The rising edge of WR loads the multiplexer address-
ing information The sampling period for the assigned posi-
tive input is maintained for the duration of the acquisition
time (t

) i e

approximately 6 to 8 clock cycles after the

rising edge of WR

An acquisition window of 6 clock cycles is available to allow
the voltage on the capacitor array to settle to the positive
analog input voltage Any change in the analog voltage on a
selected positive input before or after the acquisition win-
dow will not effect the A D conversion result

In the simplest case the array’s acquisition time is deter-
mined by the R

(9 kX) of the multiplexer switches the

stray input capacitance C

(3 5 pF) and the total array (C

)

and stray (C

) capacitance (C

48 pF) For a

large source resistance the analog input can be modeled as
an RC network as shown in

Figure 5

The values shown

yield an acquisition time of about 1 1 ms for 10-bit unipolar
or 10-bit plus sign bipolar accuracy with a zero-to-full-scale
change in the input voltage External source resistance and
capacitance will lengthen the acquisition time and should be
accounted for Slowing the clock will lengthen the acquisi-
tion time thereby allowing a larger external source resist-
ance