Texas Instruments TMS320C6000 User Manual

Page 56

Glossary

A-5

Glossary

external interrupt:

A hardware interrupt triggered by a specific value on a

pin.

external memory interface (EMIF):

Microprocessor hardware that is used

to read to and write from off-chip memory.

fetch packet:

A contiguous 8-word series of instructions fetched by the CPU

and aligned on an 8-word boundary.

flag:

A binary status indicator whose state indicates whether a particular

condition has occurred or is in effect.

FLASH:

The FLASH ROM API Module.

frame:

An 8-word space in the cache RAMs. Each fetch packet in the cache

resides in only one frame. A cache update loads a frame with the re-
quested fetch packet. The cache contains 512 frames.

global interrupt enable bit (GIE):

A bit in the control status register (CSR)

that is used to enable or disable maskable interrupts.

host:

A device to which other devices (peripherals) are connected and that

generally controls those devices.

host port interface (HPI):

A parallel interface that the CPU uses to commu-

nicate with a host processor.

HPI:

See host port interface; see also HPI module.

HPI module:

HPI is an API module used for configuring the HPI registers.

Functions are provided for reading HPI status bits and setting interrupt
events.

index:

A relative offset in the program address that specifies which of the

512 frames in the cache into which the current access is mapped.