Renesas Emulation Pod M30620T2-RPD-E - Manual (Page 62)

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Figure 5.10 Timing requirements
V
CC
= 3 V
Memory expansion mode and microprocessor mode
Common to "with wait" and "no-wait" (actual MCU)
Common to "with wait" and "no-wait" (this product)
Note 1. P0
0
to P5
2
will be high-impedance status regardless of the input level of BYTE pin and
ports P4
0
to P4
3
function selection bit (PM06) of the processor mode register 0.
Note 2. This product will be high-impedance delaying by 2.5 cycles than an actual MCU.
Note 3. The setup time of HOLD is defined by the startup of BSLK, differently from that of
actual MCUs.
Conditions:
• V
CC
=3 V
• Input timing voltage: V
IL
= 0.6 V, V
IH
= 2.4 V
• Output timing voltage: V
OL
= 1.5 V, V
OH
= 1.5 V
BCLK
BCLK
P0, P1, P2,
P3, P4,
P5
0 to P5 2
HOLD input
HOLD input
P0, P1, P2,
P3, P4,
P5
0 to P5 2
HLDA output
HLDA output