Figure 5.5 timing requirements – Renesas Emulation Pod M30620T2-RPD-E User Manual
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Figure 5.5 Timing requirements
V
CC
= 5 V
Common to "with wait" and "no-wait" (actual MCU)
BCLK
Common to "with wait" and "no-wait" (This product)
BCLK
Note 1. P0
0
to P5
2
will be high-impedance status regardless of the input level of BYTE pin and
ports P4
0
to P4
3
function selection bit (PM06) of the processor mode register 0.
Note 2. This product will be high-impedance delaying by 2.5 cycles than an actual MCU.
Note 3. The setup time of HOLD is defined by the startup of BSLK, differently from that of
actual MCUs.
Conditions:
• V
CC
=5 V
• Input timing voltage: V
IL
= 1.0 V, V
IH
= 4.0 V
• Output timing voltage: V
OL
= 2.5 V, V
OH
= 2.5 V
P0, P1, P2,
P3, P4,
P5
0
to P5
2
HOLD input
HOLD input
P0, P1, P2,
P3, P4,
P5
0
to P5
2
HLDA output
HLDA output