Renesas SuperH Family E10A-USB - Manual (Page 53)

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Table 2.12 Measurement Items (cont)
Classification Type Measurement Item Option Note
Operand bus
performance
(cont) Waited
cycle Waited cycles for
operand fetch
(READ) WOR The number of wait cycles by a
memory access (read) of an
operand.
Waited cycles for
operand fetch
(WRITE) WOW The number of wait cycles by a
memory access (write) of an
operand.
Waited cycles for
operand cache miss
(READ) WCMR The number of wait cycles by
an operand cache miss (read)
(however, the number of wait
cycles of cache FIII is included
due to contention).
Waited cycles for
operand cache miss
(WRITE) WCMW The number of wait cycles by
an operand cache miss (write).
System bus
performance
(only available
for Ch3 and
Ch4) System bus Number of requests RQ The number of valid bus cycles
(cells) is counted by the
system bus clock.
Number of
responses
RS The number of valid bus cycles
(cells) is counted by the
system bus clock.
Waited cycles for
request WRQ The cycles for an issued
request (req), that no
acceptance signal (gnt) is
issued to, are counted by the
system bus clock.
Even if the waits are issued
simultaneously for multiple
requests, they are counted as
1.
Waited cycles for
response WRS The cycles for an issued
response (r_req), that no
acceptance signal (r_gnt) is
issued to, are counted by the
system bus clock.
Even if the waits are issued
simultaneously for multiple
requests, they are counted as
1.