Renesas M32R-FPU User Manual
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Table of contents
Document Outline
- REVISION HISTORY
- Table of contents
- CHAPTER 1 CPU PROGRAMMIING MODEL
- CHAPTER 2 INSTRUCTION SET
- CHAPTER 3
INSTRUCTIONS
- 3.1 Conventions for instruction description
- 3.2 Instruction description
- ADD
- ADD3
- ADDI
- ADDV
- ADDV3
- ADDX
- AND
- AND3
- BC
- BCLR
- BEQ
- BEQZ
- BGEZ
- BGTZ
- BL
- BLEZ
- BLTZ
- BNC
- BNE
- BNEZ
- BRA
- BSET
- BTST
- CLRPSW
- CMP
- CMPI
- CMPU
- CMPUI
- DIV
- DIVU
- FADD
- FCMP
- FCMPE
- FDIV
- FMADD
- FMSUB
- FMUL
- FSUB
- FTOI
- FTOS
- ITOF
- JL
- JMP
- LD
- LD24
- LDB
- LDH
- LDI
- LDUB
- LDUH
- LOCK
- MACHI
- MACLO
- MACWHI
- MACWLO
- MUL
- MULHI
- MULLO
- MULWHI
- MULWLO
- MV
- MVFACHI
- MVFACLO
- MVFACMI
- MVFC
- MVTACHI
- MVTACLO
- MVTC
- NEG
- NOP
- NOT
- OR
- OR3
- RAC
- RACH
- REM
- REMU
- RTE
- SETH
- SETPSW
- SLL
- SLL3
- SLLI
- SRA
- SRA3
- SRAI
- SRL
- SRL3
- SRLI
- ST
- STB
- STH
- SUB
- SUBV
- SUBX
- TRAP
- UNLOCK
- UTOF
- XOR
- XOR3
- APPENDICES
- INDEX