Renesas M32R-FPU - Manual (Page 114)

3
3-76 M32R-FPU Software Manual (Rev.1.01)
MULWHI MULWHI
DSP function instruction
Multiply
word and high-order halfword
[Mnemonic]
MULWHI Rsrc1,Rsrc2
[Function]
Multiply
accumulator = ( ( signed ) Rsrc1 * ( signed short ) ( Rsrc2 >> 16 ) );
[Description]
MULWHI multiplies the 32 bits of Rsrc1 and the high-order 16 bits of Rsrc2, and stores the
result in the accumulator.
The LSB of the multiplication result is aligned with the LSB of the accumulator, and the portion
corresponding to bits 0 through 15 of the accumulator is sign-extended. The 32 bits of Rsrc1 and
high-order 16 bits of Rsrc2 are treated as signed values.
The condition bit (C) is unchanged.
[EIT occurrence]
None
[Encoding]
Rsrc1 32 bits
Rsrc2 x
0 15 16 31
0 15 16 31 32 47 48 63
high-order 16 bits
Value in accumulator after the
execution of the MULWHI instruction Sign extension
src1 0011 MULWHI Rsrc1,Rsrc2 src2 0010
INSTRUCTIONS
3.2 Instruction description