SLS Audio NEEK Board Support Package uClinux - Manual (Page 9)

System Level Solutions 1
1. Introduction
uClinux NEEK Board support package (BSP) provides developers with the easiest
and fastest way to create embedded applications on the NEEK kit (target) using
the uClinux operating system. This combination of hardware, firmware, and
software form a complete package for building, downloading, and testing
applications developed on a host machine:
• Install the uClinux board support package (BSP) on the host machine.
• Connect Ethernet and JTAG cable between host and target for serial
communication
• Build the custom Linux kernel for the NEEK board
• Start writing application code.
When ready to see your application in action, just download it to the NEEK
board. Now you can test and debug the kernel and application.
1.1 Software
uClinux NEEK BSP is the combination of uClinux, IP core drivers and
applications developed by SLS Corporation. Current version of the BSP supports
VGA, TPC, SD Card, Ethernet, PS/2 and I
2
S IP.
uClinux is a port of the Linux for MMU less processor. So many different
architectures are supported by uClinux. It has almost all necessary powers as an
embedded operating system. This document is based on kernel version 2.6.27.
Visit
www.uclinux.org for more information.
1.2 Hardware
1.2.1 Target processor
This bsp is targeted for Nios2.Nios2 is a soft core FPGA processor. It is 32 bit
RISC general purpose processor. Nios II processor system is equivalent to a
microcontroller or “Computer on a chip” that includes a processor and a
combination of peripherals and memory on a single chip. The term “Nios II
processor system” refers to a Nios II processor core, a set of on-chip peripherals,
on-chip memory, and interfaces to off-chip memory, all implemented on a Single
Altera device. Like a microcontroller family, all Nios II processor systems use a
consistent instruction set and programming model.
1.2.2 NEEK Kit (Nios Embedded Evaluation kit)
The NEEK kit includes feature reach development board having Cyclone III
EP3C25F324 FPGA, 256-Mbit DDR SDRAM, 1-Mbyte Synchronous SRAM,