Sony DVS-9000-C User Manual
Page 31
1-23
DVS-9000/9000SF
S800 (A-10) : MONITOR reset switch
The reset switch that is used to reset the monitor during
maintenance through the terminal.
SL1700 (C-6), SL1701 (C-6), SL1702 (C-6) : JTAG Chain switching
chains. Connect these slit lands to open or to close them so
that the following statuses can be obtained.
SL1700 SL1701 SL1702
Status
Short Open Open
The chain of CPLD only is established.
Open Short Short
All of the JTAG devices are connected
in chain.
CN900 (A-9) : TERMINAL pin
during maintenance.
Conforms to RS-232C.
CN1700 (A-5) : ISP common connector
Used only for production in the assembly factory. Used for
program writing into the JTAG device with ISP.
E1 (A-5), E2 (P-12), E3 (P-9), E4 (R-4), E5 (N-1), E6
(J-12), E7 (J-9), E8 (H-4), E9 (H-1), E10 (B-9), E11
(B-4) : GND terminal
respective check terminals.
TP100, TP101 (A-4) :
+
+
+
+
+1.8 V check terminal
+1.8 V-1 and 2 measuring terminal.
TP200 (A-3) :
+
+
+
+
+3.3 V check terminal
+3.3 V measuring terminal.
TP201 (A-3) :
+
+
+
+
+12 V check terminal
+12 V measuring terminal.
TP400 (N-11) : VD (vertical sync) signal check terminal
VD signal measuring terminal.
TP401 (N-11) : HD (horizontal sync) signal check
terminal
HD signal measuring terminal.
TP402 (N-11) : FLOE (Field Odd Even) signal
check terminal
FLOE signal measuring terminal.
TP403 (P-11) : CKX (control timing) signal check terminal
CKX signal measuring terminal.
TP406 (M-9) : VDO signal check terminal
VDO signal measuring terminal.
TP407 (M-10) : HDO signal check terminal
HDO signal measuring terminal.
TP408 (P-10) : FDO signal check terminal
FDO signal measuring terminal.
TP409 (P-10) : CKXO signal check terminal
CKXO signal measuring terminal.
TP900 (F-9) : SYS_CLK signal check terminal
Use to check the SYSTEM CLOCK signal.
TP901 (J-8) : CPU_CLK signal check terminal
Use to check the CPU CLOCK signal.
TP902 (K-8) : CPU_H CLK signal check terminal
Use to check the CPU H CLOCK signal.
1-8. Checks on Completion of Installation