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Figure 5.1 near-end loopback block diagram, Figure 5.2 far loopback block diagram, Smsc – SMSC FlexPWR LAN8720 User Manual

Page 52: Link partner x x

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Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

Datasheet

Revision 1.0 (05-28-09)

52

SMSC LAN8720/LAN8720i

DATASHEET

5.3.8.1

Near-end Loopback

Near-end loopback is a mode that sends the digital transmit data back out the receive data signals for
testing purposes as indicated by the blue arrows in

Figure 5.1

.The near-end loopback mode is enabled

by setting bit register 0 bit 14 to logic one.

A large percentage of the digital circuitry is operational near-end loopback mode, because data is
routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The COL
signal will be inactive in this mode, unless collision test (bit 0.7) is active. The transmitters are powered
down, regardless of the state of TXEN.

5.3.8.2

Far Loopback

Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in

Figure 5.3

. The far loopback mode is enabled by setting bit register 17 bit 9 to logic one. In this mode,

data that is received from the link partner on the MDI is looped back out to the link partner. The digital
interface signals on the local MAC interface are isolated.

5.3.8.3

Connector Loopback

The LAN8720/LAN8720i maintains reliable transmission over very short cables, and can be tested in
a connector loopback as shown in

Figure 5.3

. An RJ45 loopback cable can be used to route the

Figure 5.1 Near-end Loopback Block Diagram

Figure 5.2 Far Loopback Block Diagram

SMSC

Ethernet Transceiver

10/100

Ethernet

MAC

CAT-5

XFMR

Digital

RXD

TXD

Analog

RX

TX

X

X

Far-end system

SMSC

Ethernet Transceiver

10/100

Ethernet

MAC

CAT-5

XFMR

Digital

RXD

TXD

Analog

RX

TX

Link

Partner

X

X

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