Silicon Image SiliconDrive SSD-D32G(I)-4300 - Manual (Page 26)

E LECTRICAL S PECIFICATION SSD-D XXX (I)-4300 D ATA S HEET
S ILICON S YSTEMS P ROPRIETARY
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
All unauthorized use and/or reproduction is prohibited.
4300D-00DSR P AGE 17 F EBRUARY 27, 2009
Ultra DMA Data Burst Timing Requirements
The following figures and table describe the requirements for the Ultra DMA
(UDMA) data burst timing.
Figure 6: Initiating a UDMA Data-In Burst
Note: The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE,
and IORDY:DDMARDY-:DSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
DMARQ
(device)
DMACK-
(host)
STOP
(host)
HDMARDY-
(host)
DSTROBE
(device)
DD(15:0)
t
ZAD
DA0, DA1, DA2,
CS0-, CS1-
t
UI
t
ZAD
t
ACK
t
ACK
t
ENV
t
ENV
t
ZIORDY
t
FS
t
FS
t
DVS t
AZ
t
DVH
t
ACK