Intel 8 LAN - Manual (Page 13)

13
ICH8—NVM Information Guide
1.4.15 Shared Initialization Control (Word 13h)
This word controls general initialization values.
Table 11. Shared Initialization Control (Word 13h)
Bit Name Default Description
15:14 SIGN 10b
Valid Indication
This is a 2-bit field indicating whether a valid NVM is present to the
MAC. If this field does not equal 10b, the MAC does not read the
NVM data and uses default values for device configuration.
00b = Invalid NVM.
01b = Invalid NVM.
10b = Valid NVM present.
11b = Invalid NVM.
13:11 Reserved 010b These bits are reserved and should be set to 010b.
10 Reserved 1b Reserved. Always set to 1b.
9 PHY PD Ena 1b
For ICH8 designs that support an ACBS implementation using LAN
Power Control (LAN_PHYPC), this bit enables or disables PHY power
down.
0b = PHY power down feature is disabled.
1b = PHY power down feature is enabled to power down at DMoff/
D3 without Wake on LAN.
This bit is loaded to the PHY Power Down Enable bit in the
CTRL_EXT register.
8 Reserved 0b This bit is reserved and should be set to 0b.
7:6 PHYT 00b
This field indicates the PHY device type.
00b = 82566 PHY - GLCI mode
01b = Reserved
10b = 82562V PHY - PCIe mode, LCI mode
11b = Reserved
This field is reflected in the PHYTYPE field in the Status register.
5 Reserved 0b Reserved. Must be set to 0b.
4 FRCSPD 0b
Force Speed Enable
0b = Normal operation.
1b = Use ICH8 speed.
3 FD 0b
Force Duplex
0b = Normal operation.
1b = Use ICH8 speed.
2 CLK_CNT_1_16 1b
This bit is loaded to the CTRL_EXT.EnaKumCK16 bit and enables
the reduction of the internal JCLK to one-sixteenth of the external
NJCLK at the GLCI interface in Gigabit Ethernet mode.
0b = Reduction is disabled.
1b = Reduction is enabled.
1 CLK_CNT_1_4 0b
This bit enables the automatic reduction of DMA frequency. It is
mapped to STATUS[31].
0b = Automatic reduction disabled.
1b = Automatic reduction enabled.
0
Dynamic Clock
Gating
1b
Dynamic Clock Gating
0b = Disable.
1b = Enable.