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Intel AN430TX User Manual

Page 26

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AN430TX SPECIFICATION UPDATE

20

7.

Revision of Section 1.6.1.1, EDO DRAM

The following will be added to the end of this section:

EDO DIMM should meet the Intel 60 ns 64-bit 3.3 V unbuffered EDO DIMM v1.2 specification.

CAUTION

Due to loading anomalies, using EDO DIMMs with a n x 4 DRAM base in the AN430TX motherboard
is not recommended. For example, a DIMM that uses sixteen 16 Mbit x 4 devices should not be
used.

8.

Revision of Section 1.8.1, Serial Ports

This section will be replaced in its entirety as follows:

The motherboard has one 9-pin D-Sub serial port connector located on the back panel, and one keyed 10-pin
header located on the motherboard for cabling to the back panel. The 16540 and 16550A compatible UARTs
allow data transfers at speeds up to 115.2 Kbaud with BIOS serial port support.

9.

Revision of Section 1.13.3, Clear CMOS (J9C1-A)

This section will be replaced in its entirety as follows:

Allows CMOS settings to be reset to default values by moving the jumper from pins 4-5 to pins 5-6 and
turning the system on. When the system reports that “NVRAM cleared by jumper”, the system can be turned
off, and the jumper should be returned to the 4-5 position to restore normal operation. Default is for this
jumper to be on pins 4-5.

Caution: This procedure should only be done if, after a BIOS update, the system does not boot to a point
where Setup can be entered or if, after CMOS default settings have been restored from within the Setup
program, the system does not boot to the operating system.

10.

Revision of Section 1.16.1, Power Supply Considerations

This section will be replaced in its entirety as follows:

For typical configurations, the motherboard is designed to operate with at least a 200 W power supply (see
Section 5.1 for the specification). A higher-wattage power supply should be used for heavily-loaded
configurations. The power supply must comply with the following recommendations found in the indicated
sections of that specification:

The potential relation between 3.3VDC and +5VDC power rails (Section 4.2)

All timing parameters (Section 4.2.1.3)

All voltage tolerances (Section 4.2.2)