2 system p, 1 system p hardware overview, 2 system p hardware architecture – IBM Novell 10 SP1 EAL4 User Manual
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In this mode, applications may access:
•
64-bit flat linear addressing
•
8 new general-purpose registers (GPRs)
•
8 new registers for streaming Single Instruction/Multiple Data (SIMD) extensions (SSE, SSE2 and
SSE3)
•
64-bit-wide GPRs and instruction pointers
•
uniform byte-register addressing
•
fast interrupt-prioritization mechanism
•
a new instruction-pointer relative-addressing mode.
For architectural details about all System x models, and for detailed information about individual components
such as memory, cache, and chipset, refer to the “Accessories & Upgrades” section at
USB (except keyboard and mouse), PCMCIA, and IEEE 1394 (Firewire) devices are not supported in the
evaluated configuration.
3.2 System p
The IBM System p systems are PowerPC, POWER5 and POWER5+ processor-based systems that provide
high availability, scalability, and powerful 64-bit computing performance.
For more detailed information about the System p hardware, refer to the System p hardware website at
3.2.1 System p hardware overview
The IBM System p servers offer a range of systems, from entry level to enterprise class. The high-end
systems offer support for gigabytes of memory, large RAID configurations of SCSI and fiber channel disks,
and options for high-speed networking. The IBM System p servers are equipped with a real-time hardware
clock. The clock is powered by a small battery, and continues to tick even when the system is switched off.
The real-time clock maintains reliable time for the system. For the specification of each of the System p
servers, refer to the corresponding data sheets on the System p literature website:
For a detailed look at various peripherals such as storage devices, communications interfaces, storage
interfaces, and display devices supported on these System p models, refer to the Linux on POWER website.
3.2.2 System p hardware architecture
The IBM System p servers are powered by PowerPC™, POWER5™ and POWER5+™ processors. For
detailed specification information for each of these processors, refer to the PowerPC processor documentation
at
and POWER documentation at
For architectural details about all System p models, and for detailed information about individual components
such as memory, cache, and chipset, refer to the IBM System p technical documentation at
or
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