Channel a/b timing settings static tread value, Trd phase0 adjustment, Trd phase1 adjustment – GIGABYTE GA-EP45-UD3LR User Manual
Page 42: Trd phase2 adjustment, Trd phase3 adjustment, Trd2rd(different rank), Twr2wr(different rank), Twr2rd(different rank), Trd2wr(same/diff rank), Dimm1 clock skew control
Channel a/b timing settings static tread value, Trd phase0 adjustment, Trd phase1 adjustment | Trd phase2 adjustment, Trd phase3 adjustment, Trd2rd(different rank), Twr2wr(different rank), Twr2rd(different rank), Trd2wr(same/diff rank), Dimm1 clock skew control | GIGABYTE GA-EP45-UD3LR User Manual | Page 42 / 112 This manual is related to the following products: