Sundance SMT942 - Manual (Page 14)

User Manual SMT942 Page 14 of 55 Last Edited: 23/08/2011 17:25:00
0x3E DACab Register 0xE. Read-back (FPGA Register) DACab Register 0xE.
DACcd Section
0x40 DACcd Register 0x0. Read-back (FPGA Register) DACcd Register 0x0.
0x41 DACcd Register 0x1. Read-back (FPGA Register) DACcd Register 0x1.
… ...
0x4D DACcd Register 0xD. Read-back (FPGA Register) DACcd Register 0xD.
0x4E DACcd Register 0xE. Read-back (FPGA Register) DACcd Register 0xE.
Figure 5 – Register Memory Map.
Register Descriptions
3.4.2 Control Register 0x1.
Control Register 0x01
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Sync (chcd) TxEnable
(chcd)
Sync
(chab)
TxEnabl
e (chab)
Chcd_Read
nWrite
Chab_Rea
dnWrite
Clk_Readb
ack
Default
0 Chcd
trigger
selection
Chdc
internal
trigger
Chab
trigger
selectio
n
Chab
internal
trigger
Chcd
update
Chab
update
clk update
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Clock Register 0 0x10
Setting Bit 0 Description clk update clock chip register update
0 0 No action.
1 1 All clock registers are sent to the clock chip via its serial interface.
Setting Bit 1 Description chab update channel a and b register update
0 0 No action.
1 1 All registers (chab) are sent to the converter via its serial interface.
Setting Bit 2 Description chcd update channel c and d register update
0 1 No action.
1 1 All registers (chcd) are sent to the converter via its serial interface.
Setting Bit 4 Description chab Internal trigger
0 0 No action.
1 1 Starts the data flow (converter chab).
Setting Bit 5 Description chab trigger selection
0 0 Trigger from control register selected.
1 1 Trigger from external source selected.
Setting Bit 6 Description chcd Internal trigger
0 0 No action.
1 1 Starts the data flow (converter chcd).