Sundance SMT942 - Manual (Page 13)

User Manual SMT942 Page 13 of 55 Last Edited: 23/08/2011 17:25:00
3.4.1.2 Reading and Writing Registers
Control packets are sent to the SMT942 over Comport3. This is a bi-directional
interface. The format of a ‘Read Packet’ is the same as that of a write packet.
Host
Fixed Sequence
SMT942
ComPort 3
Byte 0
Read/Write Address Byte 1
Read/Write Data Byte 3
Read/Write Data Byte 4
1) Write Packet
Figure 4 – Control Register Read Sequence.
3.4.1.3 Memory Map
The write packets must contain the address where the data must be written to and
the read packets must contain the address where the required data must be read.
The following figure shows the memory map for the writable and readable Control
Registers on the SMT942:
Address Writable Registers Readable Registers
0x00 Reserved. Reserved.
0x01 Board Control Register. Firmware Version.
0x02 Reserved. Clock Readback Register.
0x03 Reserved. Board Status Register
Clock Section
0x10 Clock Register 0x0. Read-back (FPGA Register) Clock Register 0x0.
0x11 Clock Register 0x1. Read-back (FPGA Register) Clock Register 0x1.
… …
0x28 Clock Register 0x18. Read-back (FPGA Register) Clock Register 0x18.
0x29 Clock Register 0x19. Read-back (FPGA Register) Clock Register 0x19.
0x2A Clock Readback Address Register (LSB)
0x2B Clock Readback Address Register (MSB)
DACab Section
0x30 DACab Register 0x0. Read-back (FPGA Register) DACab Register 0x0.
0x31 DACab Register 0x1. Read-back (FPGA Register) DACab Register 0x1.
… ...
0x3D DACab Register 0xD. Read-back (FPGA Register) DACab Register 0xD.