IBM BDM-610000049 - Manual (Page 81)

BDM-610000049 Rev G Chapter 4: Using the cpuModule 71
Watchdog Timer Control
The cpuModule includes a watchdog timer, which provides protection against programs “hanging”, or getting
stuck in an execution loop where they cannot respond correctly. When enabled, the watchdog timer must be
periodically reset by your application program. If it is not refreshed before the time-out period expires, it will
cause a hardware reset of the cpuModule.
The watchdog time-out period is typically 1.1 seconds, but can vary between 550 ms and 1.65 seconds. Because
of operating system latency, it is recommended that the watchdog be refreshed at half of the period, or every
275 ms.
Before using the Watchdog timer, it must be enabled in the BIOS setup utility. When it is disabled in the BIOS,
the watchdog register does not appear in I/O space and it will not generate an a reset.
Three functions have been implemented on the cpuModule for controlling watchdog timer control. These are:
• Arm: The watchdog timer can be enabled by writing a 1 to bit 7 of I/O port 0x455. To ensure
compatability with future designs, you should read the register and only change the bit you need to
change.
• Disarm: The watchdog timer is disabled by writing a 0 to bit 7 of I/O port 0x455. To ensure
compatability with future designs, you should read the register and only change the bit you need to
change.
• Refresh : The watchdog timer is refreshed by reading from I/O port 0x455. After you enable the
watchdog timer, you must refresh it at least once every 550 ms.
Note Enabling the watchdog timer in the BIOS does not actually arm it. The watchdog timer can be
armed by accessing I/O address 455h, as explained below.
Table 53 Watchdog Timer Control I/O Address 455h
D7 D6 D5 D4 D3 D2 D1 D0
Watchdog Enable
0=Watchdog timer is disabled and will not
generate an interrupt
1=Watchdog Timer is enabled and needs
to be refreshed
Reserved