Mitsubishi Motors DS5000TK - Manual (Page 129)

USER’S GUIDE
050396 128/173
129
EXPANDED DATA MEMORY TIMING
The timing for the Expanded Data Memory access cycle
is illustrated in Figures 15–5 and 6. Accesses to Data
Memory on the Expanded Bus will occur any time that a
MOVX instruction is executed that references a Data
Memory location that is mapped outside the area which
has been assigned to the Expanded Bus via the Parti-
tion and Range.
When a MOVX instruction is used with the Data Pointer
register (e.g., MOVX @DPTR) to access a Data
Memory location on the Expanded Bus, a full 16–bit ad-
dress will be generated to the external memory. The
16–bit address is generated on P2 and P0 which are the
same pins as for a Program Memory fetch from Expand-
ed Memory. The contents of the SFR latch for Port 2 will
not be modified, however, during the execution of a Data
Memory fetch cycle on the Expanded Bus. If the MOVX
instruction is not followed by another instruction requir-
ing a cycle on the Expanded Bus, then the original con-
tents of the Port 2 SFR latch will appear once again dur-
ing the next machine cycle.
Multiplexed address/data information is output on Port 0
during the execution of a Data Memory cycle on the Ex-
panded Bus. The falling edge of ALE can be used to
latch the lower eight bits of address information into an
external transparent latch (e.g., 74LS373 or equiva-
lent). During the second cycle of a MOVX instruction,
the first ALE pulse will not be generated so that valid ad-
dress information will remain in the latch and be pres-
ented to the external memory device for the duration of
the cycle. Port 0 is written with all 1’s (0FFH) so that the
original information contained in this register is lost.
Also, Port 0 pins are driven with internal buffers when 1’s
are output during Expanded Data Memory cycles.
When a MOVX instruction is used with an indirect regis-
ter address (e.g., MOVX @R0) for the same purpose,
only an 8–bit address will be generated for the current
instruction. This 8–bit address will appear on Port 0,
while the contents of the SFR latch for Port 2 will remain
on Port 2.
When data is to be read from Data Memory on the Ex-
panded Bus, the external RD pin will be activated during
the second machine cycle of the MOVX instruction. A
complete RD cycle, including activation of ALE and RD,
takes twelve clock oscillator periods. PSEN is inactive
during this machine cycle. This cycle is illustrated in Fig-
ure 15–5. When the MOVX instruction specifies a write
operation to the external memory device, the WR signal
will be activated as shown in Figure 15–6. Data is output
on Port 0 just before WR is activated and remains valid
until it goes back to its inactive level at the conclusion of
the cycle.