Avago Technologies ACPL-C870-000E - Manual (Page 2)

2
Schematic
Figure 3 shows the evaluation board schematic. In a typical voltage sensing implementation, a resistive voltage divider
is used to scale the DC-link voltage to suit the input range of the voltage sensor. Power terminals P1 and P2 are used to
connect to the DC-link voltage across nodes L1 and L2 to be monitored. This voltage, denoted as V
L1
as L2 is connected
to the reference point GND1, is scaled down through a resistive divider consists of resistors R1 through R4 in series. On
this board, R4 has a fixed value of 10 k Ω, although it can be replaced by another value, if desired.
Figure 3. The ACPL-C87x evaluation board schematic
Given that the voltage sensor ACPL-C87x’s nominal input voltage for V
IN
is 2 V, a user needs to choose resistors R1, R2
and R3 according to Equation 1.
R4
10k, 1%
V DD1
1
V
IN
2
SHDN
3
GND1
4 GND2 5
V OUT-
6
V
OUT+
7
V DD2
8
U1
ACPL-C87X
0.47 µF
C3
0.47
C4
GND2 GND1
100 nF
C2
GND1
100 nF
C5
GND2
22 nF
C1
GND2
R7
10K, 1%
R8
10K, 1%
1 nF C8
1 nF C9
R10
10K, 1% 0.1 µ F C11
GND2
C7
1 nF
R9
10K, 1%
C6
1 nF
GND2
100K
R14
20K
R12
1 µF
C13
GND2
GND2
VDD2
-V in
1
+V in
4
+V out
5
-V out
7
U3
NKE0505DC
VDD1
V out
GND1
L1
L2
1
2
3
4
5
6
7
8
9
10
P7
Header
1
2
P2
Power Terminal
R2
Leave blank
R1
Leave blank
R3
Leave blank
2
3
6
U4
OPA237UA
Put an area of through-holes for prototyping
ANODE 1
NC 2
CATHODE 3 GND
4
V O
5
V CC
6
U2
ACPL-W50L
R5
10k
R6
700
VDD1
GND1
GND2
VDD2
V DD2
GND2
V out
GND2
SHDN
SHDN
FB 1 GND
2
DNC
3
IN
4
OUT 5
U5
LT6650CS5(IS5)
VDD2
1K
R11
1 nF
C14
1 µF
C15
GND2
V ref = 0.4V*(1+(R12+R Pot )/R14) = 0.48 to 0.52 V
1
2
P1
Power Terminal
1
2
3
default position: Pin 1-2
P4
Jumper GND2
1
2
3
default position: Pin 1-2
P3
Jumper
2
1
3 R13
R Pot 10k
TP2
TP1
TP3
TP4
TP7
TP8
TP5
TP6
V+
V-
GND2
V ref
V ref
V ref
1
2
3
default position: Pin 1-2
P6
Jumper
1
2
3
default position: Pin 1-2
P5
Jumper
V+
V-
C12
GND2
VDD2
V+
100 nF
C10
GND2
GND2
OUT
1
2 3 6 7
IN
8
GND
U6
LM78L05ACM
VS+_SEL
VS-_SEL
REF-SEL
µF
7
4
For example, if V
L1
= 600 V, then the combined value of R1, R2 and R3 = 2990 k Ω.
Choosing resistors is flexible. One method is to combine several resistors to match the target value; e.g., 2 M Ω, 430 kΩ
and 560 k Ω resistors make up 2990 kΩ exactly. In this way, V
IN
of 2 V corresponds to V
L1
of 600 V. However, in the cases
that V
L1
has a different value from 600 V, specific resistance values might be difficult to find. Another method is to round
up the target value to a convenient value 3 M Ω to make choosing resistors easier; e.g., 1 MΩ is a common value and 3
pieces of it make 3 M Ω. In this way, the scaling relationship needs some fine tune. In the same example with V
L1
= 600 V,
R1+R2+R3 = 3 M Ω, and R4 = 10 kΩ, V
IN
is solved to be 1.993 V.
After deciding resistance for R1 through R3, surface mount type devices can be mounted on the footprints provided. In
case only through-hole type resistors are available, the prototyping area can be used instead.
The down-scaled input voltage is filtered by the anti-aliasing filter formed by R4 and C1 with corner frequency of 723 Hz
[1] and then sensed by the ACPL-C87x. A differential output voltage that is proportional to the input voltage is created
on the other side of the optical isolation barrier.
Note: 1. The total value of R1 through R3 in series is usually much larger than R4, therefore neglected in calculation.
Following the isolation amplifier, an OPA237 configured as a difference amplifier converts the differential signal to a
single-ended output. This stage can be configured to further amplify the signal, if required, and form a low-pass filter
to limit the bandwidth. In this circuit, the difference amplifier is designed for a gain of 1 with a low-pass filter corner fre-
quency of 8 kHz. Resistors R9 and R10 can be selected for a different gain. The bandwidth can be reduced by increasing
capacitance for C6 and C8.
- Equation 1