Avago Technologies SAS 9211-4i Host Bus Adapter - Manual (Page 4)

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LSI SAS 9211-4i PCI Express to 6Gb/s SAS HBA User Guide
October 2014 Overview
LSI SAS 9211-4i PCI Express to 6Gb/s SAS HBA User Guide
1 Overview
The LSI® SAS 9211-4i PCI Express® (PCIe®)-to-Serial Attached SCSI (SAS) host bus adapter (HBA), hereinafter referred to
as the LSI SAS 9211-4i HBA, provides high-performance internal storage connectivity for servers and workstations. The
LSI SAS 9211-4i HBA provides four lanes of 6Gb/s SAS connectivity and is matched with four lanes of PCIe 2.0 5Gb/s
performance. The low-profile design of the SAS HBA includes a full-height bracket and low-profile mounting bracket
that creates a universal fit for any server. The LSI SAS 9211-4i HBA is based on the Fusion-MPT™ -architected LSI
SAS
2004 controller that integrates the latest enhancements in PCIe 2.0 technology and 6Gb/s SAS technology.
The LSI SAS 9211-4i HBA has onboard Flash memory for the firmware, and BIOS and NVSRAM for Integrated RAID
support (RAID 0, RAID 1, RAID 10, and RAID 1E).
2 HBA Features
This section lists the LSI SAS 9211-4i HBA features.
 Implements one LSI SAS 2004 four-port 6Gb/s to PCIe 2.0 controller
 Supports four-lane, full-duplex PCIe 2.0 performance
 Supports four internal 6Gb/s SATA+SAS ports
 Supports SATA and SAS link rates of 1.5Gb/s, 3.0Gb/s, and 6.0Gb/s
 Provides one x4 internal mini-SAS connector (SFF-8087)
 Supports passive cable
 Supports Integrated RAID (RAID 0, RAID 1, RAID 10, and RAID 1E)
 Supports up to 256 SATA or SAS end devices
 Offers a full-height bracket and low-profile bracket
 Provides activity LEDs
 Provides a universal asynchronous receiver/transmitter (UART) debug/diagnostic port
3 Functional Descriptions
3.1 PCIe
PCIe is a high-speed standard local bus for point-to-point interfacing of I/O components to the processor and the
memory subsystems in a high-end personal computer (PC). The LSI SAS 2004 controller chip contains the PCIe
functionality for the LSI SAS 9211-4i HBA. The LSI SAS 2004 controller chip connects directly to the PCIe bus and
generates timing and protocol in compliance with the PCIe specifications.