Sundance SMT365E - Manual (Page 9)

Version 2.1 Page 9 of 26 SMT365e User Manual
EMIF Control Registers
The DSP has two external memory interfaces (EMIF) which are 64 bits wide and 16
bits wide.
The DSP contains several registers that control the external memory interface
(EMIF). A full description of these registers can be found in the
DSP C6000
Peripherals Reference Guide .
The standard bootstrap will initialise these registers to use the following resources:
Memory space
(EMIFA)
Resource Address range
Internal program memory
(1MB) 0x00000000 - 0x000FFFFF
CE0 SDRAM 0x80000000 - 0x8FFFFFFF
CE1 Virtex 0x90000000 - 0x9FFFFFFF
Memory space
(EMIFB)
Resource Address range
CE0 Flash paging control 0x60000000 – 0x60000200
CE1 4MB Flash (1
st
half) 0x64000000 – 0x640FFFFF
CE2 4MB Flash (2
nd
half) 0x68000000 – 0x680FFFFF
CE3 FPGA Configuration control 0x6C000000 – 0x6C000002
SDRAM
Memory space CE0 is used to access 256MB of SDRAM over EMIFA.
The speed of the SDRAM is dependent on the processor variant. Using the C6416,
the SDRAM will operate at 133MHz maximum. It operates at one sixth of the core
clock speed.
The EMIFA CE0 memory space control register should be programmed with the
value 0x000000D0 (64 bits SDRAM).