Sundance SMT365E - Manual (Page 20)

Version 2.1 Page 20 of 26 SMT365e User Manual
Serial Ports & Other C60 I/O
The C60 contains various I/O ports. These signals are connected to a 0.1” pitch DIL
pin header. The pin-out of this connector is shown here:
P
O
DR0 FSR0 DX0 FSX0 CLKR0 CLKX0 CLKS0 CLKS1
URA3
CLKX1
URA4
CLKR1
URA2
URA1 URA0
L
A
DR2 FSR2 DX2 FSX2 CLKR2 CLKX2 CLKS2
GPIO8
DX1
UXA4
FSX1
UXA3
FSR1
UXA2
DR1
UXA1
UXA0
R
I
URD0 URD1 URD2 URD3 URD4 URD5 URD6 URD7 URCLK URENB URCLAV URSOC
S
A
UXD0 UXD1 UXD2 UXD3 UXD4 UXD5 UXD6 UXD7 UXCLK UXENB UXCLAV UXSOC
T
I
NC GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 V33 V33 TTL2 TTL3
O
N
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GND GND TTL0 TTL1
FPGA and CPLD JTAG
The following shows the pin-outs for JP2 (CPLD) and JP3 (FPGA) JTAG connectors:
Signal Pin Pin Signal
V33 1 4 TMS
TCK 2 5 TDO
GND 3 6 TDI