Sundance SMT361 - Manual (Page 9)

Version 2.7 Page 9 of 23 SMT361 SMT361A User Manual
TMS320C64xx
The processor will run with zero wait states from internal SRAM.
An on-board crystal oscillator provides the clock used for the DSP which then
multiplies this by 12 internally.
The TIM configuration feature is fully implemented. This provides a single open-
collector line that can be held low until software configuration has been completed.
Boot Mode
The SMT361 is configured to use the following boot sequence each time it is taken
out of reset:
1. The processor copies a bootstrap program from the first part of the flash
memory into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT361 then performs the following
operations:
1. All relevant DSP internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance Digital Buses. This
step must have been completed before data can be sent to the ComPort from
external sources such as the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the four
communication ports until data appears on one of them. The bootstrap will
then load a program in boot format from that port; the loader will not read data
arriving on other ports. See “Application Development” for details of the boot
loader format;
4. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is
around 1s for a SMT361 (400MHz clock).
A typical time to wait after releasing the board reset should be in excess of this delay,
but no damage will result if any of the I/Os are used before they are fully configured.
In fact, the ComPort will just produce a not ready signal when data is attempted to be
transferred during this time.