Sundance SMT361 - Manual (Page 10)

Version 2.7 Page 10 of 23 SMT361 SMT361A User Manual
EMIF Control Registers
The C64xx has two external memory interfaces (EMIFs). One of these is 64 bits
wide, the other 8 bits.
The DSP contains several registers that control the external memory interfaces
(EMIFs). A full description of these registers can be found in the C6x Peripherals
Reference Guide[1].
The standard bootstrap will initialise these registers to use the following resources:
Memory space
(EMIFA)
Resource Address range
Internal program memory
(1Mbyte) 0x00000000 - 0x000FFFFF
CE0 SDRAM 0x80000000 - 0x81FFFFFF
CE1 Virtex 0x90000000 - 0x91FFFFFF
Memory space
(EMIFB)
Resource Address range
CE1 2Mbyte flash (1 st half) 0x64000000 – 0x640FFFFF
CE2 2Mbyte flash (2 nd half) 0x68000000 – 0x680FFFFF
SDRAM
Memory space CE0 is used to access 32MB of SDRAM over EMIFA. The SDRAM
operates at EMIF clock speed. It is typically 100MHz for the SMT361 and 120MHz for
the SMT361A.
FLASH
A 2MByte Flash ROM device is connected to the DSP EMIFB.
The ROM holds boot code for the DSP, configuration data for the FPGA, and optional
user-defined code.
A software protection algorithm is in place to prevent programs accidentally altering
the ROM’s contents. Please contact Sundance for further information about re-
programming this device via the support forum.