Sundance FC201 - Manual (Page 8)

Page 8 of 8
Revision 0.4
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: [email protected]
www.sundancedsp.com
The FC201 component presents as a pure-FPGA ‘task’, and implements the following interface:
Port Name Valid
Width
Direction Implementation Description
ADC_IN 16 Input FPGA Real time domain data
COEFF_IN 32 Input FPGA Coefficient tuple load {offset, gain,
delay)
ADC_OUT 16 Output FPGA Corrected, saturated, delayed, real time
domain data
Table 1 - FC201 Interfaces
Additional port descriptions are provided below:
ADC_IN
Data values are 16-bit extended twos-complement. Only bits (15 downto 0)
are significant, higher order bits are ignored.
COEFF_IN
Data values are accepted as a 3-word tuple: offset, gain and sample delay.
The data format for offset/gain is Q15.16 (signed, 15-bit integer, 16-bit
fractional)
3
. The format for delay is an unsigned 4-bit integer, representing an
amount of sample delay. Loading coefficients causes a reset of the module.
ADC_OUT
Data values are 16-bit extended twos-complement. The values saturate to
+32767/-32768 as part of the offset/gain operation. If a non-zero delay is
given, the output samples will be taken from a 16-tap shift-register. The
higher-order output bits (31 downto 16) are sign extended from bit 15.
5.1. System Integration Considerations
The DAQ calibration ‘tasks’ are placed on the FPGA hosting the channel capture. This FPGA
needs to be supported by Diamond/FPGA in order for the tasks to be integrated.
MODULE FPGA Slices BRAM MPY F
MAX
Notes
3
See: http://en.wikipedia.org/wiki/Fixed-point_arithmetic , “Fixed Point Nomenclature”,
http://www.superkits.net/whitepapers/Fixed%20Point%20Representation%20&%20Fractional%20Math.pdf , and
http://focus.ti.com/lit/ug/spru565b/spru565b.pdf (appendix A.2)