Sundance FC201 User Manual
Page 6
Page 6 of 6
Revision 0.4
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email:
www.sundancedsp.com
4.
VERIFICATION
The firmware module is currently supported by two types of test benches. In all cases,
compilation is performed using gmake (distributed with CCS3.0 or greater)
2
.
Unit Test Benches
A C- Reference Model is implemented as a Diamond/DSP Task. This model produces a bit-
exact representation of the operations performed by the FPGA task. The code is as follows
(provided in fc201\fc201_mdl.c):
uint32_t in, out;
int32_t d0_q15p0;
int64_t d1_q16p16;
int64_t d2_q31p32;
int32_t d3_q15p0;
d0_q15p0 = (signed)(in & 0xFFFF);
d1_q16p16 = (d0_q15p0<<16) + offset_q15p16
d2_q31p32 = d1_q16p16 * gain_q15p16
d3_q15p0 = (int32_t)( d2_q31p32 >> 32 );
if( (d2_q31p32>>31) & 1 )
d3_q15p0 += (d2_q31p32 < 0) ? -1 : 1
if( d3_q15p0 > SHRT_MAX ) d3_q15p0 = SHRT_MAX
else if( d3_q15p0 < SHRT_MIN ) d3_q15p0 = SHRT_MIN;
out = (uint32_t)d3_q15p0;
This implementation of this model also correctly accounts for the pipeline depth (4 samples)
which is observed at the output (this is above any additional delay samples introduced by the
delay coefficient).
Applications are provided to perform unit tests on the C reference as well as the FPGA
implementation on a supported DSP module (the C reference model executes on the DSP, while
the FPGA implementation executes on the FPGA attached to the DSP).
To use the test benches, use ProcType.exe to define the DEFAULT processor type for your
3L/Diamond hardware platform. Be sure to select a supported “hybrid” DSP/FPGA module,
such as the SMT365-8-2, etc. Execute the fc201_mdl.app, and fc201_unit.app. This
2
Only gmake has the necessary syntax to effectively implement the build system. Contact Sundance DSP for
assistance if your installation lacks CCS.