Sundance FC201 User Manual
Page 7
Page 7 of 7
Revision 0.4
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email:
www.sundancedsp.com
will generate the files ‘output_FC201m.dat' and 'output_FC201u.dat' files
respectively. These files should be IDENTICAL.
Next, execute the fc201_integrity.app. This application generates test vectors
continuously, providing the same data to both the FPGA implementation and the C-Reference
model. The resulting output is compared to ensure a bit-exact operation. This test bench can
execute indefinitely to ensure coverage of all input byte codes.
Resource and Performance Analysis Benches
A mechanism to obtain the resource utilization of the FC201 core is provided. The basic
principle is to generate a “baseline” implementation of the target FPGA that contains a ‘stub’.
The ‘stub’ has all the same inputs and outputs, but is a trivial implementation of the FPGA task.
This “baseline” is compared to a real instantiation of the FC201 module. The stub FPGA task is
provided as ‘fc201\fc201_base.fcd’.
Comparing the two MAP report files and subtracting the Slices, BRAM and MPY in use
provides an accurate real-word estimate of the resources used by the FC201 module.
Finally, Diamond application configuration files are provided which enable the FC201 module to
be instantiated into a supported single (stand-alone) FPGA board. By connecting the dataflow
inputs (ADC_IN and ADC_OUT) of the FC201 to SDB resources, and the COEFF_IN to the
default Comport (CP3, typically) resource, a hardware reference is created which can be added to
any system and operated at line rate.
The configuration files and makefile for accomplishing these are provided in the analysis\
folder.
5.
FC201 – ADC/DAC Calibration
A calibration operation is required to normalize the output of each ADC/DAC (DAQ) within a
multi-DAQ system. Variations in the manufacturing process of the DAQs and the surrounding
circuitry can introduce voltage offsets and sampling gain variations on each channel. Further,
external systems connected to the DAQs may not have complete control over all process
parameters. Finally, when acquiring signals among multiple channels and multiple boards,
(fixed) delays in the sampling clock may occur.
Each FC201 instance allows any digital data channel to be corrected at the rate that the data is
produced. It acts as a ‘digital filter’ to transform the data stream. The FC201 component can
manipulate samples in magnitude and time. It is the responsibility of the end-user application to
determine the appropriate coefficients provided to the FC201 component in order to operate
properly.