Sundance FC201 User Manual
Page 5
Page 5 of 5
Revision 0.4
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email:
www.sundancedsp.com
In most cases, it is useful to provide some amount of elastic buffering before and after the FC201
task in order to help close timing in the FPGA design. This can be accomplished as follows:
! declare tasks
!
task fifo1
ins=1 outs=1
file="..\fifo\fifo8.fcd"
task ogd1
ins=2 outs=1
file="..\fc201\fc201.fcd"
task fifo2
ins=1 outs=1
file="..\fifo\fifo8.fcd"
!
! place tasks on FPGA
!
place fifo1
place ogd1
place fifo2
!
! connect dataflow
!
connect C1
fifo1[0]
connect ?
fifo1[0]
ogd1[0]
connect C2
connect ?
ogd1[0]
fifo2[0]
connect C3
fifo2[0]
Note: When implementing on some FPGA devices, a slower clock may be needed.
In order to close timing on some (slow) FPGA device/speed grades, the task may need to run
under a slower clock. To do this, use Diamond's facility to generate a custom clock, and provide
this clock to each FC201 instance.
See the 3L/Diamond User Guide v3.1.3 pg. 306 for additional details.
For example:
! Use a slower clock for the UUT
!
clock slow processor=
!
! place tasks on FPGA
!
place ogd1
clock=slow