Sundance SMT391 - Manual (Page 9)

Version 1.5 Page 9 of 18 SMT391 User Manual
Figure 3 – Module Clock Structure.
Description of the Clock Tree
The main clock source of the module is a UMC 600MHz to 1200MHz voltage
controlled oscillator. The frequency range of the VCO is adjustable with a National
PLL. The output of the VCO + PLL combination is passed through a Maxim high
frequency comparator with an LVPECL output to form the main system clock. In
addition to this clock there is a clock synthesizer on the module that can generate a
50 to 950 MHz clock. This clock is ideal for testing purposes. Alternatively the user
can provide the module with an external LVPECL clock – one input for each channel.
The clock synthesiser does not provide a clock as clear as the VCO does. Therefore
the performances of the module degrade when using the clock synthesiser.
The FPGA controls the LVPECL multiplexers that choose the final clock (clock
synthesizer, PLL+VCO, or external). A copy of this clock is fed to each channel of the
ADC. Another copy is divided by 8 (to give a 125MHz LVPECL clock) and fed into the
FPGA. (In the current firmware implementation this copy of the clock is not used by
the firmware design. The two clocks originating from the ADC is used by the design.
This clock can also only be the VCO or the synthesizer clock, not one of the external
clocks.)
The ADC clock determines the sampling rate of the ADC. The ADC buffers and
divides this clock by two (or four) to provide a 500MHz LVDS clock for each de-
multiplexed data channel (or a 250MHz DDR clock depending on the way the ADC is
configured). These two clocks are used to clock the ADC data into the FPGA.
When data is transmitted over the RSL links there must be a reference clock on the
receiving module that is closely matched in frequency to the transmitting clock. This
is important to insure that there will be no data over or under run. Due to this
requirement data can only be transmitted over the RSL interface when the on-board
VCO clock is used.
All clock circuitry is implemented on the daughter card. The four clocks that enter the
FPGA are passed down from the daughter card to the main module. An additional
125MHz oscillator is located on the main module. This oscillator is used as the
system clock for the FPGA design.
SLB
The SMT391 connects to a base module (for example a SMT338-VP) via the SLB
connector. Refer to the SLB specification document for more information.