Sundance SMT391 - Manual (Page 8)

Version 1.5 Page 8 of 18 SMT391 User Manual
Figure 2 – AC-coupled Analogue Input stage.
Clock structure
There is an integrated clock generator (PLL+VCO clock or synthesized clock) on the
module. The user can either use this clock or provide the module with an external
clock (input via MMBX connectors, one for each channel).
External Clock Module Clock
FPGA
PLL
Comparitor
Clock
Control
Voltage Controlled
Oscillator
TTL to LVPECL
LVPECL
Buffers
External Clock Input
(MMBX)
4:2 Mux with Dual Output
ADC
Clock
Div 8
Ch A
C
lo
c
k
Ch B
C
lo
c
k
LVDS
SerDes
Clock
Sys
Clock
DLL
RSL
Clock
DLL
Diagram Key:
500 MHz LVDS Clock
125 MHz LVPECL Clock
1000 MHz LVPECL Clock