Sundance SMT364 - Manual (Page 8)

Version 1.0 Page 8 of 37 SMT364 User Manual
Architecture Description.
The module consists of a Xilinx Virtex-II FPGA , four Analog Devices (14-bit
monolithic sampling Analog-to-Digital converters) AD6645.
The AD6645 is a 14-bit monolithic sampling analog-to-digital converter. The chip
provides CMOS-compatible digital outputs. It is the Analog Devices’ fourth generation
of wideband ADCs. The AD6645 maintains outstanding AC performance up to input
frequencies of 200 MHz, which makes it suitable for multi-carrier 3G applications.
The AD6645 is able to sample from 30 up to 105 MHz. Nevertheless, it is possible to
reduce that rate by performing decimation on the data flow.
Parallel busses connect ADCs to the FPGA, which is responsible for transferring
samples from the converters. Two on-board frequency synthesizers generate
differential encode lines (sampling clocks) to feed the converters; two connectors for
two external clocks is also available. Each analogue signal input to the ADCs goes
through an extra stage, which can be an opamp (DC coupling) or an RF transformer
(AC coupling). The option must be defined when ordering a SMT364. ADCs can be
coupled together. i.e. they have the same sampling clock or have separate clocks,
one external and one coming from the on-board clock synthesizer.
The Xilinx FPGA Virtex-II is configured via a 6-pin JTAG header or from the on-board
Xilinx PROM (
XC18V04 ) at startup. The default configuration mode is from a PROM,
which contains the standard modes of operation (as described in this document). An
on-board LED indicates that the FPGA is configured. Both devices, FPGA and
PROM are in the JTAG chain.
Four Communication links (ComPorts) following the Texas Instrument C4x standard
are connected to the FPGA and will be used to receive control words or for other
purpose. They can achieve transfers at up to 20Mbytes/s.
Two full SHB connectors (60-pin) are accessible from the FPGA. Both are output only
and carry samples from ADCs. There are two ADC data-flows per SHB connector).
Please refer to the
SHB specifications for more details about ways connectors can be
configured. Both SHB can be implemented as either two 16-bit interfaces or a single
32-bit interface. In the case of a 32-bit interface, both ADCs must receive the same
sampling clock signal.
Four LEDs are driven by the FPGA. Four LVTTL I/Os for general purpose are also
available. No clamping diodes to 3.3 Volts and ground are available on the board to
avoid damaging pads on the FPGA. It is therefore to the customer to make sure the
signals connected to these I/Os are LVTTL and don’t show any overshoots.
External Clock, trigger and analogue input signals are all single-ended. External
connections to the board are all 50-Ohm terminated. External triggers have clamping
diodes to 3.3V and to Ground to avoid damaging the FPGA they are connected to.
A global reset signal is mapped to the FPGA from the top TIM connector to reset the
FPGA and reload the FPGA