Sundance SMT364 - Manual (Page 11)

Version 1.0 Page 11 of 37 SMT364 User Manual
to have external trigger signal synchronised to the sampling clock. This external
trigger also goes thought 7 latch stages.
Communication Ports (ComPorts).
The SMT364 provides 4 physical ComPorts: 0, 1, 3 and 4. The default bit stream
provided implements ComPort 4 (Input at reset) to load control registers. A physical
connection to a ComPort 0, 1 or 2 (Output at reset) is therefore necessary, to an
SMT365 for instance. Please report to the part dealing with ComPorts
(Communication Ports (ComPorts).) in this document for more details.
External triggering.
Two external trigger connectors (J6 and J12 – see Figure 8 - Connector Location.)
are available on the board to trigger converters from an external source. The
selection is made via a control register, where channel selection can also be set.
There is one trigger per pair of ADC channels.
Triggering consists in enabling or stopping the converters. This is available and
accurate as long as the triggering signals are synchronised on the sampling clock.
Triggering signals can be set as active high or low in via the control register.
Each trigger input is clamped to 3.3 and Ground to avoid damaging the FPGA I/Os.
This is achieved by using single diodes (
BAV99 ). These diodes can support as
maximum, 200mA of forward current and 70 Volts of reverse voltage. It is to the
customer to consider this when building a system using an SMT364.
LEDs.
Seven LEDs (Figure 8 - Connector Location.) are available on the board. Four
(denoted 0, 1, 2, and 3 on the PCB – top left) of them, green, are driven by the
FPGA. In the default bitstream, they indicate what follows:
0 -> Flashing under the ADCA sampling clock (it can be useful to check that
the LED is flashing when using an external sampling clock signal),
1 -> Flashing under the ADCB sampling clock,
2 -> Flashing under the ADCB sampling clock,
3 -> Flashing under the ADCB sampling clock.
Two green LEDs, located at the bottom left and right of the board indicate the status
of the power supplies. Both should be on when the board is under power.
A red LED located on the top right of the board indicated when the FPGA is not
programme. In normal operation, i.e. J1 fitted (Figure 8 - Connector Location.), it
flashes once at power-up and after a module reset.
Just after a reset (TIM or FPGA Global Reset), the LEDs display the Firmware
version.