Sundance SMT364 - Manual (Page 18)

Version 1.0 Page 18 of 37 SMT364 User Manual
An SHB interface can be 8,16 or 32-bit wide.
The default FPGA firmware implements 2 16-bit interfaces.
FPGA Pinout.
###############################
# Constraint File Virtex II for SMT364
#Author:Philippe ROBERT
#$Date:23.07.2002
#$Version: 1.0 - Original draft NET "adcd_data<4>" LOC = "W17" ;
#$Date: 09.09.2002
# $Version: 1.1 - CP1 removed and
Clock synthesizer changed
#$Date: 23.07.2002
NET "adcd_data<0>" LOC = "AB19" ;
#$Version 1.0 generated with
FloorPlanner
#$Version 1.1 01/04/03 - pinout
reviewed
# $Version 1.2 28/04/03 - CommPort 1
and 4 added
# (c) Sundance Multiprocessor
Technology #
###############################
# Start of Constraints extracted by
Floorplanner from the Design
# ADCD
NET "adcd_rdy_gclk" LOC = "AB12" ;
NET "adcd_rdy" LOC = "AA16" ;
NET "adcd_ovr" LOC = "V17" ;
NET "adcd_data<13>" LOC = "AB16"
;
NET "adcd_data<12>" LOC = "W16" ;
NET "adcd_data<11>" LOC = "Y16" ;
NET "adcd_data<10>" LOC = "V16" ;
NET "adcd_data<9>" LOC = "V15" ;
NET "adcd_data<8>" LOC = "AA17" ;
NET "adcd_data<7>" LOC = "AB17" ;
NET "adcd_data<6>" LOC = "AA18" ;
NET "adcd_data<5>" LOC = "AB18" ;
NET "adcd_data<3>" LOC = "Y17" ;
NET "adcd_data<2>" LOC = "W18" ;
NET "adcd_data<1>" LOC = "Y18" ;
# ADCC
NET "adcc_rdy_gclk" LOC = "Y12" ;
NET "adcc_rdy" LOC = "AA13" ;
NET "adcc_ovr" LOC = "Y15" ;
NET "adcc_data<13>" LOC = "AB13" ;
NET "adcc_data<12>" LOC = "U13" ;
NET "adcc_data<11>" LOC = "V13" ;
NET "adcc_data<10>" LOC = "W13" ;
NET "adcc_data<9>" LOC = "Y13" ;
NET "adcc_data<8>" LOC = "AA14" ;
NET "adcc_data<7>" LOC = "AB14" ;
NET "adcc_data<6>" LOC = "W14" ;
NET "adcc_data<5>" LOC = "Y14" ;
NET "adcc_data<4>" LOC = "U14" ;
NET "adcc_data<3>" LOC = "V14" ;
NET "adcc_data<2>" LOC = "AA15" ;
NET "adcc_data<1>" LOC = "AB15" ;
NET "adcc_data<0>" LOC = "W15" ;
# ADCB