Sundance SMT349 - Manual (Page 14)

Version 2.1 Page 14 of 32 SMT349 User Manual
SDB0 and SDB1 on the FPGA are presented on the TIM's SHB connectors, SHBA
and SHBB respectively. The interface for these connectors is not implemented in the
default firmware since it is not used for standard application.
7.3 LED
The SMT349 has 7 LEDs. LED5 displays the state of the FPGA DONE pin. This LED
is off when the FPGA is configured (DONE=1) and on when it is not configured
(DONE=0). This LED should go on when the board is first powered up and go off
when the FPGA has been successfully programmed, using the contents of the on-
board PROM. If the LED does not light at power-on, check that you have the
mounting pillars and screws fitted properly. If it stays on, the DSP is not booting
correctly, or is set to boot in a non-standard way.
There are 4 LEDs connected directly to the FPGA as standard IO. LED1 is flashing
constantly (except when FPGA kept reset) at the on-board crystal rate (50MHz).
LED2 ON means that the IF/RF clock synthesizer has successfully locked after being
programmed. LED3 and LED4 are respectively address bits 1 and 0 of the last
control word received.
Two LEDs (6 and 7) show that the power supplies of 3.3V and 5 are working.
7.4 Standard LVTTL IO pins
There are two set of pins (J17 and JX6) which are connected to the FPGA and can
be accessed by the user. These pins are compliant with the LVTTL standard.
The default FPGA design provided routes the IF/RF clock synthesizer lock signal to
pin5 of JX6 in order to be probed if necessary. A ‘1’ means the IF/RF clock
synthesizer has locked successfully after being programmed.
7.5 FPGA
The SMT349 is populated with a Xilinx Virtex FPGA (XC2V1000-4). This device
controls major functions on the module, like Comports communications, memory and
clock management. SHB connectors can also be controlled through it, but they are
not in the default software.
This FPGA requires configuration after power-up and after a module reset. This
operation is possible due to the on-board Xilinx PROM. This operation can be done
automatically when jumper JX2 is fitted. If JX2 is not fitted, the FPGA is not
automatically loaded, and the JTAG interface may be used to program the FPGA
without conflict.
The PROM is originally programmed with a default bit stream, which implements the
features described in this document.
7.6 Memory
The SMT349 is also populated with some NtSRAM memory . It is 32-bit wide and to
store two 16-bit samples at the same address at up 160 MHz. Its size is 1