Sundance SMT338 - Manual (Page 7)

Version 1.5 Page 7 of 19 SMT338 User Manual
The SMT338 provides 32 differential input pairs and 8 differential output pairs on-board.
The 32 receiver pairs have 2 of their TTL outputs connected to two Global clock
buffers of the Virtex to be able to use its DLL capabilities.
The Virtex provides four independent Global Clock Buffers, which allow the use of 4
programmable DLLs to produce waveforms with a wide range of frequencies and duty cycles.
Figure 3 is a detailed view of the Differential signal connections to the FPGA and the clock
buffers assignments.
Figure 3: Global Clock Buffers assignments in the Virtex
FPGA
XCVxxxx
BG352
50 way High Density Diff_Con2 50 way High Density Diff_Con1
DIFF1
15
Clk 1
TTL
5
5
Gnd
BANK0
BANK4 BANK5
BANK1
SDB B
22
40 way IDC
SDB_ConA
SDB A
22
Clk A
BoardClk
40 way IDC
SDB_ConB
Clk B
TTL
5
DIFF2
15
5
Gnd
Clk 2
30 30
2 2
1 1
DIFF2
4
DIFF1
4
Diff Conv Diff Conv
8 8